| From e9820b57258070c818d42906e2ef8344113d4aac Mon Sep 17 00:00:00 2001 |
| From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Date: Sat, 5 Nov 2016 00:59:37 +0300 |
| Subject: [PATCH 257/299] ARM: dts: r8a7745: add IRQC support |
| |
| Describe the IRQC interrupt controller in the R8A7745 device tree. |
| |
| Based on the original (and large) patch by Dmitry Shifrin |
| <dmitry.shifrin@cogentembedded.com>. |
| |
| Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 28c43fbb3ca0a9a8f547aece94dac8d791358444) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/boot/dts/r8a7745.dtsi | 19 +++++++++++++++++++ |
| 1 file changed, 19 insertions(+) |
| |
| --- a/arch/arm/boot/dts/r8a7745.dtsi |
| +++ b/arch/arm/boot/dts/r8a7745.dtsi |
| @@ -62,6 +62,25 @@ |
| IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| + irqc: interrupt-controller@e61c0000 { |
| + compatible = "renesas,irqc-r8a7745", "renesas,irqc"; |
| + #interrupt-cells = <2>; |
| + interrupt-controller; |
| + reg = <0 0xe61c0000 0 0x200>; |
| + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 407>; |
| + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; |
| + }; |
| + |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | |
