blob: 21b8c063b186d5ec4a9acfcddc082cf97e324b0b [file] [log] [blame]
From be2a5ca84cd25584096191fb8ea57cda38a4a79a Mon Sep 17 00:00:00 2001
From: Hans Verkuil <hans.verkuil@cisco.com>
Date: Tue, 22 May 2018 07:33:14 -0400
Subject: [PATCH 1164/1795] media: adv7511: fix incorrect clear of CEC receive
interrupt
If a CEC message was received and the RX interrupt was set, but
not yet processed, and a new transmit was issues, then the
transmit code would inadvertently clear the RX interrupt and
after that no new messages would ever be received.
Instead it should only clear TX interrupts since register 0x97
is a clear-on-write register.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
(cherry picked from commit 00f6f92dbbeb3b98d38b26449be0df46b2e6d6a4)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/media/i2c/adv7511.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/adv7511.c b/drivers/media/i2c/adv7511.c
index 5ff25efd0f08..0dda236a3153 100644
--- a/drivers/media/i2c/adv7511.c
+++ b/drivers/media/i2c/adv7511.c
@@ -843,8 +843,8 @@ static int adv7511_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
*/
adv7511_cec_write_and_or(sd, 0x12, ~0x70, max(1, attempts - 1) << 4);
- /* blocking, clear cec tx irq status */
- adv7511_wr_and_or(sd, 0x97, 0xc7, 0x38);
+ /* clear cec tx irq status */
+ adv7511_wr(sd, 0x97, 0x38);
/* write data */
for (i = 0; i < len; i++)
--
2.19.0