| From 54e31317d4f0e0659acd8c0592de80efc497294e Mon Sep 17 00:00:00 2001 |
| From: Biju Das <biju.das@bp.renesas.com> |
| Date: Mon, 13 Nov 2017 17:43:12 +0000 |
| Subject: [PATCH 0695/1795] ARM: dts: iwg20d-q7: Enable PCIe Controller |
| |
| Enable PCIe Controller & set PCIe bus clock frequency. |
| |
| Signed-off-by: Biju Das <biju.das@bp.renesas.com> |
| Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit b3a0317e312cc6d6359c7a0854d763cde528391d) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| --- |
| arch/arm/boot/dts/iwg20d-q7-common.dtsi | 8 ++++++++ |
| 1 file changed, 8 insertions(+) |
| |
| diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi |
| index 3e4bc4d6b9d3..54470c6de891 100644 |
| --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi |
| +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi |
| @@ -96,6 +96,14 @@ |
| pinctrl-names = "default"; |
| }; |
| |
| +&pcie_bus_clk { |
| + clock-frequency = <100000000>; |
| +}; |
| + |
| +&pciec { |
| + status = "okay"; |
| +}; |
| + |
| &pfc { |
| can0_pins: can0 { |
| groups = "can0_data_d"; |
| -- |
| 2.19.0 |
| |
