| From d7aa5286201c7c2b61ae4da25355314084d4645c Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> |
| Date: Fri, 7 Jun 2013 10:47:02 +0300 |
| Subject: drm/i915: Disable trickle feed via MI_ARB_STATE for the gen4 |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| According to BSpec, trickle feed should be disabled for BW and |
| mobile CL. Those constraints seem to match all of our gen4 chipsets. |
| |
| Trickle feed is disabled via the MI_ARB_STATE register instead of |
| per plane controls on gen4. |
| |
| Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> |
| Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit 20f949670f51341f255b17ec4650fa69ba22cb87) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/intel_pm.c | 4 ++++ |
| 1 file changed, 4 insertions(+) |
| |
| diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c |
| index af6c0d15d896..d1e2e68edeb7 100644 |
| --- a/drivers/gpu/drm/i915/intel_pm.c |
| +++ b/drivers/gpu/drm/i915/intel_pm.c |
| @@ -4944,6 +4944,8 @@ static void crestline_init_clock_gating(struct drm_device *dev) |
| I915_WRITE(DSPCLK_GATE_D, 0); |
| I915_WRITE(RAMCLK_GATE_D, 0); |
| I915_WRITE16(DEUC, 0); |
| + I915_WRITE(MI_ARB_STATE, |
| + _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
| } |
| |
| static void broadwater_init_clock_gating(struct drm_device *dev) |
| @@ -4956,6 +4958,8 @@ static void broadwater_init_clock_gating(struct drm_device *dev) |
| I965_ISC_CLOCK_GATE_DISABLE | |
| I965_FBC_CLOCK_GATE_DISABLE); |
| I915_WRITE(RENCLK_GATE_D2, 0); |
| + I915_WRITE(MI_ARB_STATE, |
| + _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
| } |
| |
| static void gen3_init_clock_gating(struct drm_device *dev) |
| -- |
| 1.8.5.rc3 |
| |
