| From 1dc91cc92322c86a937405bc660332eb065d7d57 Mon Sep 17 00:00:00 2001 |
| From: Daniel Vetter <daniel.vetter@ffwll.ch> |
| Date: Thu, 13 Jun 2013 00:54:59 +0200 |
| Subject: drm/i915: explicitly set up PIPECONF (and gamma table) on haswell |
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| |
| Again we don't really support different settings, so don't let the |
| BIOS sneak stuff through. |
| |
| Since the motivation for this patch series is to ensure we have the |
| correct gamma table mode selected also add the required write to the |
| GAMMA_MODE register to select the 8bit legacy table. |
| |
| And since I find lowercase letters in #defines offensive, also |
| bikeshed those. |
| |
| Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> |
| Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit 3eff4faa9f59c581538663e3f42b9e16210cafd0) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/i915_reg.h | 6 +++--- |
| drivers/gpu/drm/i915/intel_display.c | 7 ++++--- |
| 2 files changed, 7 insertions(+), 6 deletions(-) |
| |
| --- a/drivers/gpu/drm/i915/i915_reg.h |
| +++ b/drivers/gpu/drm/i915/i915_reg.h |
| @@ -3684,9 +3684,9 @@ |
| #define _GAMMA_MODE_B 0x4ac80 |
| #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) |
| #define GAMMA_MODE_MODE_MASK (3 << 0) |
| -#define GAMMA_MODE_MODE_8bit (0 << 0) |
| -#define GAMMA_MODE_MODE_10bit (1 << 0) |
| -#define GAMMA_MODE_MODE_12bit (2 << 0) |
| +#define GAMMA_MODE_MODE_8BIT (0 << 0) |
| +#define GAMMA_MODE_MODE_10BIT (1 << 0) |
| +#define GAMMA_MODE_MODE_12BIT (2 << 0) |
| #define GAMMA_MODE_MODE_SPLIT (3 << 0) |
| |
| /* interrupts */ |
| --- a/drivers/gpu/drm/i915/intel_display.c |
| +++ b/drivers/gpu/drm/i915/intel_display.c |
| @@ -5437,13 +5437,11 @@ static void haswell_set_pipeconf(struct |
| enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
| uint32_t val; |
| |
| - val = I915_READ(PIPECONF(cpu_transcoder)); |
| + val = 0; |
| |
| - val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); |
| if (intel_crtc->config.dither) |
| val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
| |
| - val &= ~PIPECONF_INTERLACE_MASK_HSW; |
| if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
| val |= PIPECONF_INTERLACED_ILK; |
| else |
| @@ -5451,6 +5449,9 @@ static void haswell_set_pipeconf(struct |
| |
| I915_WRITE(PIPECONF(cpu_transcoder), val); |
| POSTING_READ(PIPECONF(cpu_transcoder)); |
| + |
| + I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
| + POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
| } |
| |
| static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
