| From c3cf69ab684bc7b0db033ec54b8e15daa29e991a Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> |
| Date: Thu, 22 Aug 2013 19:23:13 +0300 |
| Subject: drm/i915: Fix context size calculation on SNB/IVB/VLV |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| All the different context sizes reported in the CXT_SIZE register |
| aren't meant to be simply added together. |
| |
| While BSpec is somewhat unclear on the topic of the actual context |
| size, empirical tests have now revealed the truth. So let's add a |
| big fat comment to remind people how it all works. |
| |
| As a result of correctly interpreting CXT_SIZE, the IVB context |
| size is reduced from three pages to two, while SNB context size |
| remains at two pages. |
| |
| Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Acked-by: Ben Widawsky <ben@bwidawsk.net> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit e8016055335687b90e7cd5bbfa30e0c269417f34) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++-------- |
| 1 file changed, 15 insertions(+), 8 deletions(-) |
| |
| --- a/drivers/gpu/drm/i915/i915_reg.h |
| +++ b/drivers/gpu/drm/i915/i915_reg.h |
| @@ -1709,15 +1709,26 @@ |
| */ |
| #define CCID 0x2180 |
| #define CCID_EN (1<<0) |
| +/* |
| + * Notes on SNB/IVB/VLV context size: |
| + * - Power context is saved elsewhere (LLC or stolen) |
| + * - Ring/execlist context is saved on SNB, not on IVB |
| + * - Extended context size already includes render context size |
| + * - We always need to follow the extended context size. |
| + * SNB BSpec has comments indicating that we should use the |
| + * render context size instead if execlists are disabled, but |
| + * based on empirical testing that's just nonsense. |
| + * - Pipelined/VF state is saved on SNB/IVB respectively |
| + * - GT1 size just indicates how much of render context |
| + * doesn't need saving on GT1 |
| + */ |
| #define CXT_SIZE 0x21a0 |
| #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) |
| #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) |
| #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) |
| #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) |
| #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) |
| -#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_POWER_SIZE(cxt_reg) + \ |
| - GEN6_CXT_RING_SIZE(cxt_reg) + \ |
| - GEN6_CXT_RENDER_SIZE(cxt_reg) + \ |
| +#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ |
| GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ |
| GEN6_CXT_PIPELINE_SIZE(cxt_reg)) |
| #define GEN7_CXT_SIZE 0x21a8 |
| @@ -1727,11 +1738,7 @@ |
| #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) |
| #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) |
| #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) |
| -#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_POWER_SIZE(ctx_reg) + \ |
| - GEN7_CXT_RING_SIZE(ctx_reg) + \ |
| - GEN7_CXT_RENDER_SIZE(ctx_reg) + \ |
| - GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ |
| - GEN7_CXT_GT1_SIZE(ctx_reg) + \ |
| +#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ |
| GEN7_CXT_VFSTATE_SIZE(ctx_reg)) |
| /* Haswell does have the CXT_SIZE register however it does not appear to be |
| * valid. Now, docs explain in dwords what is in the context object. The full |
