| From 6d9c0509b381c8bae9c90fae732850dff45d1cf1 Mon Sep 17 00:00:00 2001 |
| From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Date: Tue, 28 May 2013 02:46:41 +0400 |
| Subject: sata_rcar: add 'base' local variable to some functions |
| |
| The 'base' field of 'struct sata_rcar_priv' is used very often |
| throughout the driver, so it seems worth loading it into a local |
| variable if it's used more than once in a function. |
| |
| While at it, put some unitialized variables after intialized ones for |
| aesthetic reasons. :-) |
| |
| Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Signed-off-by: Tejun Heo <tj@kernel.org> |
| (cherry picked from commit 1b20f6a9adaa4b88d520d279c3d605f65b898625) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| |
| Conflicts: |
| drivers/ata/sata_rcar.c |
| --- |
| drivers/ata/sata_rcar.c | 101 +++++++++++++++++++++++++++--------------------- |
| 1 file changed, 57 insertions(+), 44 deletions(-) |
| |
| diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c |
| index 6626a5bc..b1dd5d82 100644 |
| --- a/drivers/ata/sata_rcar.c |
| +++ b/drivers/ata/sata_rcar.c |
| @@ -130,41 +130,44 @@ struct sata_rcar_priv { |
| |
| static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv) |
| { |
| + void __iomem *base = priv->base; |
| + |
| /* idle state */ |
| - iowrite32(0, priv->base + SATAPHYADDR_REG); |
| + iowrite32(0, base + SATAPHYADDR_REG); |
| /* reset */ |
| - iowrite32(SATAPHYRESET_PHYRST, priv->base + SATAPHYRESET_REG); |
| + iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); |
| udelay(10); |
| /* deassert reset */ |
| - iowrite32(0, priv->base + SATAPHYRESET_REG); |
| + iowrite32(0, base + SATAPHYRESET_REG); |
| } |
| |
| static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val, |
| int group) |
| { |
| + void __iomem *base = priv->base; |
| int timeout; |
| |
| /* deassert reset */ |
| - iowrite32(0, priv->base + SATAPHYRESET_REG); |
| + iowrite32(0, base + SATAPHYRESET_REG); |
| /* lane 1 */ |
| - iowrite32(SATAPHYACCEN_PHYLANE, priv->base + SATAPHYACCEN_REG); |
| + iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); |
| /* write phy register value */ |
| - iowrite32(val, priv->base + SATAPHYWDATA_REG); |
| + iowrite32(val, base + SATAPHYWDATA_REG); |
| /* set register group */ |
| if (group) |
| reg |= SATAPHYADDR_PHYRATEMODE; |
| /* write command */ |
| - iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, priv->base + SATAPHYADDR_REG); |
| + iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); |
| /* wait for ack */ |
| for (timeout = 0; timeout < 100; timeout++) { |
| - val = ioread32(priv->base + SATAPHYACK_REG); |
| + val = ioread32(base + SATAPHYACK_REG); |
| if (val & SATAPHYACK_PHYACK) |
| break; |
| } |
| if (timeout >= 100) |
| pr_err("%s timeout\n", __func__); |
| /* idle state */ |
| - iowrite32(0, priv->base + SATAPHYADDR_REG); |
| + iowrite32(0, base + SATAPHYADDR_REG); |
| } |
| |
| static void sata_rcar_freeze(struct ata_port *ap) |
| @@ -180,14 +183,15 @@ static void sata_rcar_freeze(struct ata_port *ap) |
| static void sata_rcar_thaw(struct ata_port *ap) |
| { |
| struct sata_rcar_priv *priv = ap->host->private_data; |
| + void __iomem *base = priv->base; |
| |
| /* ack */ |
| - iowrite32(~SATA_RCAR_INT_MASK, priv->base + SATAINTSTAT_REG); |
| + iowrite32(~SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); |
| |
| ata_sff_thaw(ap); |
| |
| /* unmask */ |
| - iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, priv->base + SATAINTMASK_REG); |
| + iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG); |
| } |
| |
| static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) |
| @@ -509,15 +513,16 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) |
| { |
| struct ata_port *ap = qc->ap; |
| unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE; |
| - u32 dmactl; |
| struct sata_rcar_priv *priv = ap->host->private_data; |
| + void __iomem *base = priv->base; |
| + u32 dmactl; |
| |
| /* load PRD table addr. */ |
| mb(); /* make sure PRD table writes are visible to controller */ |
| - iowrite32(ap->bmdma_prd_dma, priv->base + ATAPI_DTB_ADR_REG); |
| + iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG); |
| |
| /* specify data direction, triple-check start bit is clear */ |
| - dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); |
| + dmactl = ioread32(base + ATAPI_CONTROL1_REG); |
| dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP); |
| if (dmactl & ATAPI_CONTROL1_START) { |
| dmactl &= ~ATAPI_CONTROL1_START; |
| @@ -525,7 +530,7 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) |
| } |
| if (!rw) |
| dmactl |= ATAPI_CONTROL1_RW; |
| - iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); |
| + iowrite32(dmactl, base + ATAPI_CONTROL1_REG); |
| |
| /* issue r/w command */ |
| ap->ops->sff_exec_command(ap, &qc->tf); |
| @@ -534,28 +539,30 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) |
| static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc) |
| { |
| struct ata_port *ap = qc->ap; |
| - u32 dmactl; |
| struct sata_rcar_priv *priv = ap->host->private_data; |
| + void __iomem *base = priv->base; |
| + u32 dmactl; |
| |
| /* start host DMA transaction */ |
| - dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); |
| + dmactl = ioread32(base + ATAPI_CONTROL1_REG); |
| dmactl &= ~ATAPI_CONTROL1_STOP; |
| dmactl |= ATAPI_CONTROL1_START; |
| - iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); |
| + iowrite32(dmactl, base + ATAPI_CONTROL1_REG); |
| } |
| |
| static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) |
| { |
| struct ata_port *ap = qc->ap; |
| struct sata_rcar_priv *priv = ap->host->private_data; |
| + void __iomem *base = priv->base; |
| u32 dmactl; |
| |
| /* force termination of DMA transfer if active */ |
| - dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); |
| + dmactl = ioread32(base + ATAPI_CONTROL1_REG); |
| if (dmactl & ATAPI_CONTROL1_START) { |
| dmactl &= ~ATAPI_CONTROL1_START; |
| dmactl |= ATAPI_CONTROL1_STOP; |
| - iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); |
| + iowrite32(dmactl, base + ATAPI_CONTROL1_REG); |
| } |
| |
| /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ |
| @@ -565,8 +572,8 @@ static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) |
| static u8 sata_rcar_bmdma_status(struct ata_port *ap) |
| { |
| struct sata_rcar_priv *priv = ap->host->private_data; |
| - u32 status; |
| u8 host_stat = 0; |
| + u32 status; |
| |
| status = ioread32(priv->base + ATAPI_STATUS_REG); |
| if (status & ATAPI_STATUS_DEVINT) |
| @@ -665,19 +672,20 @@ static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance) |
| { |
| struct ata_host *host = dev_instance; |
| struct sata_rcar_priv *priv = host->private_data; |
| - struct ata_port *ap; |
| + void __iomem *base = priv->base; |
| unsigned int handled = 0; |
| + struct ata_port *ap; |
| u32 sataintstat; |
| unsigned long flags; |
| |
| spin_lock_irqsave(&host->lock, flags); |
| |
| - sataintstat = ioread32(priv->base + SATAINTSTAT_REG); |
| + sataintstat = ioread32(base + SATAINTSTAT_REG); |
| sataintstat &= SATA_RCAR_INT_MASK; |
| if (!sataintstat) |
| goto done; |
| /* ack */ |
| - iowrite32(~sataintstat & 0x7ff, priv->base + SATAINTSTAT_REG); |
| + iowrite32(~sataintstat & 0x7ff, base + SATAINTSTAT_REG); |
| |
| ap = host->ports[0]; |
| |
| @@ -699,15 +707,16 @@ static void sata_rcar_setup_port(struct ata_host *host) |
| struct ata_port *ap = host->ports[0]; |
| struct ata_ioports *ioaddr = &ap->ioaddr; |
| struct sata_rcar_priv *priv = host->private_data; |
| + void __iomem *base = priv->base; |
| |
| ap->ops = &sata_rcar_port_ops; |
| ap->pio_mask = ATA_PIO4; |
| ap->udma_mask = ATA_UDMA6; |
| ap->flags |= ATA_FLAG_SATA; |
| |
| - ioaddr->cmd_addr = priv->base + SDATA_REG; |
| - ioaddr->ctl_addr = priv->base + SSDEVCON_REG; |
| - ioaddr->scr_addr = priv->base + SCRSSTS_REG; |
| + ioaddr->cmd_addr = base + SDATA_REG; |
| + ioaddr->ctl_addr = base + SSDEVCON_REG; |
| + ioaddr->scr_addr = base + SCRSSTS_REG; |
| ioaddr->altstatus_addr = ioaddr->ctl_addr; |
| |
| ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); |
| @@ -725,6 +734,7 @@ static void sata_rcar_setup_port(struct ata_host *host) |
| static void sata_rcar_init_controller(struct ata_host *host) |
| { |
| struct sata_rcar_priv *priv = host->private_data; |
| + void __iomem *base = priv->base; |
| u32 val; |
| |
| /* reset and setup phy */ |
| @@ -737,27 +747,27 @@ static void sata_rcar_init_controller(struct ata_host *host) |
| sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); |
| |
| /* SATA-IP reset state */ |
| - val = ioread32(priv->base + ATAPI_CONTROL1_REG); |
| + val = ioread32(base + ATAPI_CONTROL1_REG); |
| val |= ATAPI_CONTROL1_RESET; |
| - iowrite32(val, priv->base + ATAPI_CONTROL1_REG); |
| + iowrite32(val, base + ATAPI_CONTROL1_REG); |
| |
| /* ISM mode, PRD mode, DTEND flag at bit 0 */ |
| - val = ioread32(priv->base + ATAPI_CONTROL1_REG); |
| + val = ioread32(base + ATAPI_CONTROL1_REG); |
| val |= ATAPI_CONTROL1_ISM; |
| val |= ATAPI_CONTROL1_DESE; |
| val |= ATAPI_CONTROL1_DTA32M; |
| - iowrite32(val, priv->base + ATAPI_CONTROL1_REG); |
| + iowrite32(val, base + ATAPI_CONTROL1_REG); |
| |
| /* Release the SATA-IP from the reset state */ |
| - val = ioread32(priv->base + ATAPI_CONTROL1_REG); |
| + val = ioread32(base + ATAPI_CONTROL1_REG); |
| val &= ~ATAPI_CONTROL1_RESET; |
| - iowrite32(val, priv->base + ATAPI_CONTROL1_REG); |
| + iowrite32(val, base + ATAPI_CONTROL1_REG); |
| |
| /* ack and mask */ |
| - iowrite32(0, priv->base + SATAINTSTAT_REG); |
| - iowrite32(0x7ff, priv->base + SATAINTMASK_REG); |
| + iowrite32(0, base + SATAINTSTAT_REG); |
| + iowrite32(0x7ff, base + SATAINTMASK_REG); |
| /* enable interrupts */ |
| - iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG); |
| + iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); |
| } |
| |
| static int sata_rcar_probe(struct platform_device *pdev) |
| @@ -824,14 +834,15 @@ static int sata_rcar_remove(struct platform_device *pdev) |
| { |
| struct ata_host *host = platform_get_drvdata(pdev); |
| struct sata_rcar_priv *priv = host->private_data; |
| + void __iomem *base = priv->base; |
| |
| ata_host_detach(host); |
| |
| /* disable interrupts */ |
| - iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG); |
| + iowrite32(0, base + ATAPI_INT_ENABLE_REG); |
| /* ack and mask */ |
| - iowrite32(0, priv->base + SATAINTSTAT_REG); |
| - iowrite32(0x7ff, priv->base + SATAINTMASK_REG); |
| + iowrite32(0, base + SATAINTSTAT_REG); |
| + iowrite32(0x7ff, base + SATAINTMASK_REG); |
| |
| clk_disable(priv->clk); |
| |
| @@ -843,14 +854,15 @@ static int sata_rcar_suspend(struct device *dev) |
| { |
| struct ata_host *host = dev_get_drvdata(dev); |
| struct sata_rcar_priv *priv = host->private_data; |
| + void __iomem *base = priv->base; |
| int ret; |
| |
| ret = ata_host_suspend(host, PMSG_SUSPEND); |
| if (!ret) { |
| /* disable interrupts */ |
| - iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG); |
| + iowrite32(0, base + ATAPI_INT_ENABLE_REG); |
| /* mask */ |
| - iowrite32(0x7ff, priv->base + SATAINTMASK_REG); |
| + iowrite32(0x7ff, base + SATAINTMASK_REG); |
| |
| clk_disable(priv->clk); |
| } |
| @@ -862,14 +874,15 @@ static int sata_rcar_resume(struct device *dev) |
| { |
| struct ata_host *host = dev_get_drvdata(dev); |
| struct sata_rcar_priv *priv = host->private_data; |
| + void __iomem *base = priv->base; |
| |
| clk_enable(priv->clk); |
| |
| /* ack and mask */ |
| - iowrite32(0, priv->base + SATAINTSTAT_REG); |
| - iowrite32(0x7ff, priv->base + SATAINTMASK_REG); |
| + iowrite32(0, base + SATAINTSTAT_REG); |
| + iowrite32(0x7ff, base + SATAINTMASK_REG); |
| /* enable interrupts */ |
| - iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG); |
| + iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); |
| |
| ata_host_resume(host); |
| |
| -- |
| 1.8.4.3.gca3854a |
| |