patches.renesas/0097-sh-pfc-r8a7778-add-SDHI-support.patch

From 524fba2c4ee5dde087e35759ea8ebc8dcdd954c8 Mon Sep 17 00:00:00 2001
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Date: Thu, 18 Apr 2013 20:08:23 -0700
Subject: sh-pfc: r8a7778: add SDHI support

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 564617d2f92473031d035deb273da5374e62d0f0)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 141 +++++++++++++++++++++++++++++++++++
 1 file changed, 141 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 139f9dde..b1925cc1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1427,6 +1427,84 @@ SCIF_PFC_DAT(scif5_data_a,	TX5_A,			RX5_A);
 SCIF_PFC_PIN(scif5_data_b,	RCAR_GP_PIN(1, 15),	RCAR_GP_PIN(1, 14));
 SCIF_PFC_DAT(scif5_data_b,	TX5_B,			RX5_B);
 
+/* - SDHI macro ------------------------------------------------------------- */
+#define SDHI_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
+#define SDHI_PFC_DAT1(name, d0)			SH_PFC_MUX1(name, d0)
+#define SDHI_PFC_DAT4(name, d0, d1, d2, d3)	SH_PFC_MUX4(name, d0, d1, d2, d3)
+#define SDHI_PFC_CTRL(name, clk, cmd)		SH_PFC_MUX2(name, clk, cmd)
+#define SDHI_PFC_CDPN(name, cd)			SH_PFC_MUX1(name, cd)
+#define SDHI_PFC_WPPN(name, wp)			SH_PFC_MUX1(name, wp)
+
+/* - SDHI0 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi0_cd,		RCAR_GP_PIN(3, 17));
+SDHI_PFC_CDPN(sdhi0_cd,		SD0_CD);
+SDHI_PFC_PINS(sdhi0_ctrl,	RCAR_GP_PIN(3, 11),	RCAR_GP_PIN(3, 12));
+SDHI_PFC_CTRL(sdhi0_ctrl,	SD0_CLK,		SD0_CMD);
+SDHI_PFC_PINS(sdhi0_data1,	RCAR_GP_PIN(3, 13));
+SDHI_PFC_DAT1(sdhi0_data1,	SD0_DAT0);
+SDHI_PFC_PINS(sdhi0_data4,	RCAR_GP_PIN(3, 13),	RCAR_GP_PIN(3, 14),
+				RCAR_GP_PIN(3, 15),	RCAR_GP_PIN(3, 16));
+SDHI_PFC_DAT4(sdhi0_data4,	SD0_DAT0,		SD0_DAT1,
+				SD0_DAT2,		SD0_DAT3);
+SDHI_PFC_PINS(sdhi0_wp,		RCAR_GP_PIN(3, 18));
+SDHI_PFC_WPPN(sdhi0_wp,		SD0_WP);
+
+/* - SDHI1 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi1_a_cd,	RCAR_GP_PIN(0, 30));
+SDHI_PFC_CDPN(sdhi1_a_cd,	SD1_CD_A);
+SDHI_PFC_PINS(sdhi1_a_ctrl,	RCAR_GP_PIN(1, 5),	RCAR_GP_PIN(1, 6));
+SDHI_PFC_CTRL(sdhi1_a_ctrl,	SD1_CLK_A,		SD1_CMD_A);
+SDHI_PFC_PINS(sdhi1_a_data1,	RCAR_GP_PIN(1, 7));
+SDHI_PFC_DAT1(sdhi1_a_data1,	SD1_DAT0_A);
+SDHI_PFC_PINS(sdhi1_a_data4,	RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
+				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6));
+SDHI_PFC_DAT4(sdhi1_a_data4,	SD1_DAT0_A,		SD1_DAT1_A,
+				SD1_DAT2_A,		SD1_DAT3_A);
+SDHI_PFC_PINS(sdhi1_a_wp,	RCAR_GP_PIN(0, 31));
+SDHI_PFC_WPPN(sdhi1_a_wp,	SD1_WP_A);
+
+SDHI_PFC_PINS(sdhi1_b_cd,	RCAR_GP_PIN(2, 24));
+SDHI_PFC_CDPN(sdhi1_b_cd,	SD1_CD_B);
+SDHI_PFC_PINS(sdhi1_b_ctrl,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 16));
+SDHI_PFC_CTRL(sdhi1_b_ctrl,	SD1_CLK_B,		SD1_CMD_B);
+SDHI_PFC_PINS(sdhi1_b_data1,	RCAR_GP_PIN(1, 18));
+SDHI_PFC_DAT1(sdhi1_b_data1,	SD1_DAT0_B);
+SDHI_PFC_PINS(sdhi1_b_data4,	RCAR_GP_PIN(1, 18),	RCAR_GP_PIN(1, 19),
+				RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
+SDHI_PFC_DAT4(sdhi1_b_data4,	SD1_DAT0_B,		SD1_DAT1_B,
+				SD1_DAT2_B,		SD1_DAT3_B);
+SDHI_PFC_PINS(sdhi1_b_wp,	RCAR_GP_PIN(2, 25));
+SDHI_PFC_WPPN(sdhi1_b_wp,	SD1_WP_B);
+
+
+/* - SDH2 ------------------------------------------------------------------- */
+SDHI_PFC_PINS(sdhi2_a_cd,	RCAR_GP_PIN(4, 23));
+SDHI_PFC_CDPN(sdhi2_a_cd,	SD2_CD_A);
+SDHI_PFC_PINS(sdhi2_a_ctrl,	RCAR_GP_PIN(4, 17),	RCAR_GP_PIN(4, 18));
+SDHI_PFC_CTRL(sdhi2_a_ctrl,	SD2_CLK_A,		SD2_CMD_A);
+SDHI_PFC_PINS(sdhi2_a_data1,	RCAR_GP_PIN(4, 19));
+SDHI_PFC_DAT1(sdhi2_a_data1,	SD2_DAT0_A);
+SDHI_PFC_PINS(sdhi2_a_data4,	RCAR_GP_PIN(4, 19),	RCAR_GP_PIN(4, 20),
+				RCAR_GP_PIN(4, 21),	RCAR_GP_PIN(4, 22));
+SDHI_PFC_DAT4(sdhi2_a_data4,	SD2_DAT0_A,		SD2_DAT1_A,
+				SD2_DAT2_A,		SD2_DAT3_A);
+SDHI_PFC_PINS(sdhi2_a_wp,	RCAR_GP_PIN(4, 24));
+SDHI_PFC_WPPN(sdhi2_a_wp,	SD2_WP_A);
+
+SDHI_PFC_PINS(sdhi2_b_cd,	RCAR_GP_PIN(3, 27));
+SDHI_PFC_CDPN(sdhi2_b_cd,	SD2_CD_B);
+SDHI_PFC_PINS(sdhi2_b_ctrl,	RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6));
+SDHI_PFC_CTRL(sdhi2_b_ctrl,	SD2_CLK_B,		SD2_CMD_B);
+SDHI_PFC_PINS(sdhi2_b_data1,	RCAR_GP_PIN(4, 7));
+SDHI_PFC_DAT1(sdhi2_b_data1,	SD2_DAT0_B);
+SDHI_PFC_PINS(sdhi2_b_data4,	RCAR_GP_PIN(4, 7),	RCAR_GP_PIN(4, 8),
+				RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 26));
+SDHI_PFC_DAT4(sdhi2_b_data4,	SD2_DAT0_B,		SD2_DAT1_B,
+				SD2_DAT2_B,		SD2_DAT3_B);
+SDHI_PFC_PINS(sdhi2_b_wp,	RCAR_GP_PIN(3, 28));
+SDHI_PFC_WPPN(sdhi2_b_wp,	SD2_WP_B);
+
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(hscif0_data_a),
 	SH_PFC_PIN_GROUP(hscif0_data_b),
@@ -1471,6 +1549,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(scif4_data_c),
 	SH_PFC_PIN_GROUP(scif5_data_a),
 	SH_PFC_PIN_GROUP(scif5_data_b),
+	SH_PFC_PIN_GROUP(sdhi0_cd),
+	SH_PFC_PIN_GROUP(sdhi0_ctrl),
+	SH_PFC_PIN_GROUP(sdhi0_data1),
+	SH_PFC_PIN_GROUP(sdhi0_data4),
+	SH_PFC_PIN_GROUP(sdhi0_wp),
+	SH_PFC_PIN_GROUP(sdhi1_a_cd),
+	SH_PFC_PIN_GROUP(sdhi1_a_ctrl),
+	SH_PFC_PIN_GROUP(sdhi1_a_data1),
+	SH_PFC_PIN_GROUP(sdhi1_a_data4),
+	SH_PFC_PIN_GROUP(sdhi1_a_wp),
+	SH_PFC_PIN_GROUP(sdhi1_b_cd),
+	SH_PFC_PIN_GROUP(sdhi1_b_ctrl),
+	SH_PFC_PIN_GROUP(sdhi1_b_data1),
+	SH_PFC_PIN_GROUP(sdhi1_b_data4),
+	SH_PFC_PIN_GROUP(sdhi1_b_wp),
+	SH_PFC_PIN_GROUP(sdhi2_a_cd),
+	SH_PFC_PIN_GROUP(sdhi2_a_ctrl),
+	SH_PFC_PIN_GROUP(sdhi2_a_data1),
+	SH_PFC_PIN_GROUP(sdhi2_a_data4),
+	SH_PFC_PIN_GROUP(sdhi2_a_wp),
+	SH_PFC_PIN_GROUP(sdhi2_b_cd),
+	SH_PFC_PIN_GROUP(sdhi2_b_ctrl),
+	SH_PFC_PIN_GROUP(sdhi2_b_data1),
+	SH_PFC_PIN_GROUP(sdhi2_b_data4),
+	SH_PFC_PIN_GROUP(sdhi2_b_wp),
 };
 
 static const char * const hscif0_groups[] = {
@@ -1543,6 +1646,41 @@ static const char * const scif5_groups[] = {
 	"scif5_data_b",
 };
 
+
+static const char * const sdhi0_groups[] = {
+	"sdhi0_cd",
+	"sdhi0_ctrl",
+	"sdhi0_data1",
+	"sdhi0_data4",
+	"sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+	"sdhi1_a_cd",
+	"sdhi1_a_ctrl",
+	"sdhi1_a_data1",
+	"sdhi1_a_data4",
+	"sdhi1_a_wp",
+	"sdhi1_b_cd",
+	"sdhi1_b_ctrl",
+	"sdhi1_b_data1",
+	"sdhi1_b_data4",
+	"sdhi1_b_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+	"sdhi2_a_cd",
+	"sdhi2_a_ctrl",
+	"sdhi2_a_data1",
+	"sdhi2_a_data4",
+	"sdhi2_a_wp",
+	"sdhi2_b_cd",
+	"sdhi2_b_ctrl",
+	"sdhi2_b_data1",
+	"sdhi2_b_data4",
+	"sdhi2_b_wp",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(hscif0),
 	SH_PFC_FUNCTION(hscif1),
@@ -1553,6 +1691,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scif3),
 	SH_PFC_FUNCTION(scif4),
 	SH_PFC_FUNCTION(scif5),
+	SH_PFC_FUNCTION(sdhi0),
+	SH_PFC_FUNCTION(sdhi1),
+	SH_PFC_FUNCTION(sdhi2),
 };
 
 static struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
1.8.4.3.gca3854a