| From bf3921a6b9fb00dae9f3aaf6c248f96266e96a65 Mon Sep 17 00:00:00 2001 |
| From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
| Date: Tue, 19 Nov 2013 01:05:23 -0800 |
| Subject: ARM: shmobile: r8a7790: tidyup clock table order |
| |
| SuperH lookups clock is using CLKDEV_CON/DEV/ICK_ID() macro |
| for a long term. |
| But in these days, the ICK clock is defined in random place. |
| This patch arranges it. |
| |
| Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit eb7a91749fc1c4fa4f011dad40e3faf4c0ca27b0) |
| (Queued by ARM-SoC for v3.14 but not yet in Linus's tree) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/mach-shmobile/clock-r8a7790.c | 13 ++++++++----- |
| 1 file changed, 8 insertions(+), 5 deletions(-) |
| |
| diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c |
| index ec6b394add4a..8c280611e3c7 100644 |
| --- a/arch/arm/mach-shmobile/clock-r8a7790.c |
| +++ b/arch/arm/mach-shmobile/clock-r8a7790.c |
| @@ -266,11 +266,6 @@ static struct clk_lookup lookups[] = { |
| CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), |
| |
| /* MSTP */ |
| - CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), |
| - CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]), |
| - CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]), |
| - CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]), |
| - CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]), |
| CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), |
| CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), |
| CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), |
| @@ -303,7 +298,15 @@ static struct clk_lookup lookups[] = { |
| CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), |
| CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), |
| CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]), |
| + |
| + /* ICK */ |
| CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]), |
| + CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), |
| + CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]), |
| + CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]), |
| + CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]), |
| + CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]), |
| + |
| }; |
| |
| #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ |
| -- |
| 1.8.5.rc3 |
| |
