| From 392c1954243ab01e46fe09e39b3dc39cc6574edd Mon Sep 17 00:00:00 2001 |
| From: Yoshikazu Fujikawa <yoshikazu.fujikawa.ue@renesas.com> |
| Date: Wed, 4 Sep 2013 12:46:08 +0900 |
| Subject: ARM: shmobile: r8a7791 SCIF support |
| |
| Add SCIF serial port support to the r8a7791 SoC by |
| adding platform devices for SCIFA0 -> SCIFA5 as well |
| as SCIFB0 -> SCIFB2 and SCIF0 -> SCIF5 together with |
| clock bindings. DT device description is excluded at |
| this point since such bindings are still under |
| development. |
| |
| Signed-off-by: Yoshikazu Fujikawa <yoshikazu.fujikawa.ue@renesas.com> |
| Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> |
| [damm@opensource.se: Forward ported to upstream, dropped holes in enum] |
| Signed-off-by: Magnus Damm <damm@opensource.se> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| |
| (cherry picked from commit e6491d08ed1d5d1e415d5371f2ff2fed67df83b0) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/mach-shmobile/clock-r8a7791.c | 36 +++++++++++- |
| arch/arm/mach-shmobile/include/mach/r8a7791.h | 1 + |
| arch/arm/mach-shmobile/setup-r8a7791.c | 82 +++++++++++++++++++++++++++ |
| 3 files changed, 118 insertions(+), 1 deletion(-) |
| |
| diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c |
| index 9929feb1b810..df3122ea4c69 100644 |
| --- a/arch/arm/mach-shmobile/clock-r8a7791.c |
| +++ b/arch/arm/mach-shmobile/clock-r8a7791.c |
| @@ -48,6 +48,7 @@ |
| #define CPG_BASE 0xe6150000 |
| #define CPG_LEN 0x1000 |
| |
| +#define SMSTPCR0 0xE6150130 |
| #define SMSTPCR1 0xE6150134 |
| #define SMSTPCR2 0xe6150138 |
| #define SMSTPCR3 0xE615013C |
| @@ -56,6 +57,7 @@ |
| #define SMSTPCR8 0xE6150990 |
| #define SMSTPCR9 0xE6150994 |
| #define SMSTPCR10 0xE6150998 |
| +#define SMSTPCR11 0xE615099C |
| |
| #define MODEMR 0xE6160060 |
| #define SDCKCR 0xE6150074 |
| @@ -118,13 +120,28 @@ static struct clk *main_clks[] = { |
| /* MSTP */ |
| enum { |
| MSTP721, MSTP720, |
| -/* MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,*/ |
| + MSTP719, MSTP718, MSTP715, MSTP714, |
| + MSTP216, MSTP207, MSTP206, |
| + MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, |
| MSTP_NR |
| }; |
| |
| static struct clk mstp_clks[MSTP_NR] = { |
| [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ |
| [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ |
| + [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ |
| + [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ |
| + [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ |
| + [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ |
| + [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ |
| + [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ |
| + [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ |
| + [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ |
| + [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ |
| + [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ |
| + [MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */ |
| + [MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */ |
| + [MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */ |
| }; |
| |
| static struct clk_lookup lookups[] = { |
| @@ -141,6 +158,23 @@ static struct clk_lookup lookups[] = { |
| CLKDEV_CON_ID("mp", &mp_clk), |
| CLKDEV_CON_ID("cp", &cp_clk), |
| CLKDEV_CON_ID("peripheral_clk", &hp_clk), |
| + |
| + /* MSTP */ |
| + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ |
| + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ |
| + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */ |
| + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), /* SCIFB1 */ |
| + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), /* SCIFB2 */ |
| + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), /* SCIFA2 */ |
| + CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), /* SCIF0 */ |
| + CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), /* SCIF1 */ |
| + CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP719]), /* SCIF2 */ |
| + CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */ |
| + CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */ |
| + CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */ |
| + CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */ |
| + CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ |
| + CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ |
| }; |
| |
| #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ |
| diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h |
| index 43b7206998da..d234b8cd9e91 100644 |
| --- a/arch/arm/mach-shmobile/include/mach/r8a7791.h |
| +++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h |
| @@ -1,6 +1,7 @@ |
| #ifndef __ASM_R8A7791_H__ |
| #define __ASM_R8A7791_H__ |
| |
| +void r8a7791_add_dt_devices(void); |
| void r8a7791_clock_init(void); |
| |
| #endif /* __ASM_R8A7791_H__ */ |
| diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c |
| index 88dcce1a6391..0de6aec3bb63 100644 |
| --- a/arch/arm/mach-shmobile/setup-r8a7791.c |
| +++ b/arch/arm/mach-shmobile/setup-r8a7791.c |
| @@ -22,10 +22,92 @@ |
| #include <linux/irq.h> |
| #include <linux/kernel.h> |
| #include <linux/of_platform.h> |
| +#include <linux/serial_sci.h> |
| #include <mach/common.h> |
| +#include <mach/irqs.h> |
| #include <mach/r8a7791.h> |
| #include <asm/mach/arch.h> |
| |
| +#define SCIF_COMMON(scif_type, baseaddr, irq) \ |
| + .type = scif_type, \ |
| + .mapbase = baseaddr, \ |
| + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
| + .irqs = SCIx_IRQ_MUXED(irq) |
| + |
| +#define SCIFA_DATA(index, baseaddr, irq) \ |
| +[index] = { \ |
| + SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ |
| + .scbrr_algo_id = SCBRR_ALGO_4, \ |
| + .scscr = SCSCR_RE | SCSCR_TE, \ |
| +} |
| + |
| +#define SCIFB_DATA(index, baseaddr, irq) \ |
| +[index] = { \ |
| + SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ |
| + .scbrr_algo_id = SCBRR_ALGO_4, \ |
| + .scscr = SCSCR_RE | SCSCR_TE, \ |
| +} |
| + |
| +#define SCIF_DATA(index, baseaddr, irq) \ |
| +[index] = { \ |
| + SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ |
| + .scbrr_algo_id = SCBRR_ALGO_2, \ |
| + .scscr = SCSCR_RE | SCSCR_TE, \ |
| +} |
| + |
| +#define HSCIF_DATA(index, baseaddr, irq) \ |
| +[index] = { \ |
| + SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ |
| + .scbrr_algo_id = SCBRR_ALGO_6, \ |
| + .scscr = SCSCR_RE | SCSCR_TE, \ |
| +} |
| + |
| +enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, |
| + SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 }; |
| + |
| +static const struct plat_sci_port scif[] __initconst = { |
| + SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ |
| + SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ |
| + SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ |
| + SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ |
| + SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ |
| + SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ |
| + SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ |
| + SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ |
| + SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */ |
| + SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */ |
| + SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */ |
| + SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */ |
| + SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */ |
| + SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */ |
| + SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */ |
| +}; |
| + |
| +static inline void r8a7791_register_scif(int idx) |
| +{ |
| + platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], |
| + sizeof(struct plat_sci_port)); |
| +} |
| + |
| +void __init r8a7791_add_dt_devices(void) |
| +{ |
| + r8a7791_register_scif(SCIFA0); |
| + r8a7791_register_scif(SCIFA1); |
| + r8a7791_register_scif(SCIFB0); |
| + r8a7791_register_scif(SCIFB1); |
| + r8a7791_register_scif(SCIFB2); |
| + r8a7791_register_scif(SCIFA2); |
| + r8a7791_register_scif(SCIF0); |
| + r8a7791_register_scif(SCIF1); |
| + r8a7791_register_scif(SCIF2); |
| + r8a7791_register_scif(SCIF3); |
| + r8a7791_register_scif(SCIF4); |
| + r8a7791_register_scif(SCIF5); |
| + r8a7791_register_scif(SCIFA3); |
| + r8a7791_register_scif(SCIFA4); |
| + r8a7791_register_scif(SCIFA5); |
| +} |
| + |
| #ifdef CONFIG_USE_OF |
| static const char *r8a7791_boards_compat_dt[] __initdata = { |
| "renesas,r8a7791", |
| -- |
| 1.8.5.rc3 |
| |