| From 3ff32b6164d7bb13e58ec52c4a8d40e2e787605a Mon Sep 17 00:00:00 2001 |
| From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Date: Sun, 18 Aug 2013 03:11:28 +0400 |
| Subject: sh_eth: get register layout from 'struct sh_eth_cpu_data' |
| |
| The register layout is a SoC characteristic, so it's wrong that it's stored |
| in the otherwise board specific platform data. Add 'register_type' field to |
| 'struct sh_eth_cpu_data', initialize it properly for each SoC, and read it |
| from this structure instead of the platfrom data from now on... |
| |
| Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| (cherry picked from commit a3153d8c41132d6fda080a4b3e53b7ee25d3c125) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/net/ethernet/renesas/sh_eth.c | 22 +++++++++++++++++++++- |
| drivers/net/ethernet/renesas/sh_eth.h | 1 + |
| 2 files changed, 22 insertions(+), 1 deletion(-) |
| |
| diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c |
| index 52ab996a..ebce05b1 100644 |
| --- a/drivers/net/ethernet/renesas/sh_eth.c |
| +++ b/drivers/net/ethernet/renesas/sh_eth.c |
| @@ -378,6 +378,8 @@ static struct sh_eth_cpu_data r8a777x_data = { |
| .set_duplex = sh_eth_set_duplex, |
| .set_rate = sh_eth_set_rate_r8a777x, |
| |
| + .register_type = SH_ETH_REG_FAST_RCAR, |
| + |
| .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, |
| .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, |
| .eesipr_value = 0x01ff009f, |
| @@ -398,6 +400,8 @@ static struct sh_eth_cpu_data r8a7790_data = { |
| .set_duplex = sh_eth_set_duplex, |
| .set_rate = sh_eth_set_rate_r8a777x, |
| |
| + .register_type = SH_ETH_REG_FAST_RCAR, |
| + |
| .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, |
| .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, |
| .eesipr_value = 0x01ff009f, |
| @@ -435,6 +439,8 @@ static struct sh_eth_cpu_data sh7724_data = { |
| .set_duplex = sh_eth_set_duplex, |
| .set_rate = sh_eth_set_rate_sh7724, |
| |
| + .register_type = SH_ETH_REG_FAST_SH4, |
| + |
| .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, |
| .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, |
| .eesipr_value = 0x01ff009f, |
| @@ -473,6 +479,8 @@ static struct sh_eth_cpu_data sh7757_data = { |
| .set_duplex = sh_eth_set_duplex, |
| .set_rate = sh_eth_set_rate_sh7757, |
| |
| + .register_type = SH_ETH_REG_FAST_SH4, |
| + |
| .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| .rmcr_value = 0x00000001, |
| |
| @@ -541,6 +549,8 @@ static struct sh_eth_cpu_data sh7757_data_giga = { |
| .set_duplex = sh_eth_set_duplex, |
| .set_rate = sh_eth_set_rate_giga, |
| |
| + .register_type = SH_ETH_REG_GIGABIT, |
| + |
| .ecsr_value = ECSR_ICD | ECSR_MPD, |
| .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, |
| .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| @@ -599,6 +609,8 @@ static struct sh_eth_cpu_data sh7734_data = { |
| .set_duplex = sh_eth_set_duplex, |
| .set_rate = sh_eth_set_rate_gether, |
| |
| + .register_type = SH_ETH_REG_GIGABIT, |
| + |
| .ecsr_value = ECSR_ICD | ECSR_MPD, |
| .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, |
| .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| @@ -626,6 +638,8 @@ static struct sh_eth_cpu_data sh7763_data = { |
| .set_duplex = sh_eth_set_duplex, |
| .set_rate = sh_eth_set_rate_gether, |
| |
| + .register_type = SH_ETH_REG_GIGABIT, |
| + |
| .ecsr_value = ECSR_ICD | ECSR_MPD, |
| .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, |
| .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| @@ -663,6 +677,8 @@ static struct sh_eth_cpu_data r8a7740_data = { |
| .set_duplex = sh_eth_set_duplex, |
| .set_rate = sh_eth_set_rate_gether, |
| |
| + .register_type = SH_ETH_REG_GIGABIT, |
| + |
| .ecsr_value = ECSR_ICD | ECSR_MPD, |
| .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, |
| .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| @@ -685,6 +701,8 @@ static struct sh_eth_cpu_data r8a7740_data = { |
| }; |
| |
| static struct sh_eth_cpu_data sh7619_data = { |
| + .register_type = SH_ETH_REG_FAST_SH3_SH2, |
| + |
| .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| |
| .apr = 1, |
| @@ -694,6 +712,8 @@ static struct sh_eth_cpu_data sh7619_data = { |
| }; |
| |
| static struct sh_eth_cpu_data sh771x_data = { |
| + .register_type = SH_ETH_REG_FAST_SH3_SH2, |
| + |
| .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| .tsu = 1, |
| }; |
| @@ -2643,10 +2663,10 @@ static int sh_eth_drv_probe(struct platform_device *pdev) |
| mdp->edmac_endian = pd->edmac_endian; |
| mdp->no_ether_link = pd->no_ether_link; |
| mdp->ether_link_active_low = pd->ether_link_active_low; |
| - mdp->reg_offset = sh_eth_get_register_offset(pd->register_type); |
| |
| /* set cpu data */ |
| mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; |
| + mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); |
| sh_eth_set_default_cpu_data(mdp->cd); |
| |
| /* set function */ |
| diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h |
| index da93f5cf..1e785281 100644 |
| --- a/drivers/net/ethernet/renesas/sh_eth.h |
| +++ b/drivers/net/ethernet/renesas/sh_eth.h |
| @@ -454,6 +454,7 @@ struct sh_eth_cpu_data { |
| void (*set_rate)(struct net_device *ndev); |
| |
| /* mandatory initialize value */ |
| + int register_type; |
| unsigned long eesipr_value; |
| |
| /* optional initialize value */ |
| -- |
| 1.8.4.3.gca3854a |
| |