| From a3b3f6c7149a441940602b15e3b7ccf0ffb02d72 Mon Sep 17 00:00:00 2001 |
| From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> |
| Date: Wed, 22 May 2013 19:46:16 +0900 |
| Subject: sh-pfc: r8a7790: Rename I2C SDA/SCL pins |
| |
| The I2C pins have been renamed in the datasheet, rename them here as |
| well. |
| |
| Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> |
| Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| (cherry picked from commit c4721249dd15684d97af76b2b10073baff90959e) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 208 +++++++++++++++++------------------ |
| 1 file changed, 104 insertions(+), 104 deletions(-) |
| |
| diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| index 95b38faf..3ddebc6b 100644 |
| --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| @@ -111,9 +111,9 @@ enum { |
| FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, |
| FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, |
| FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, |
| - FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, |
| - FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C, |
| - FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, |
| + FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, |
| + FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, |
| + FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, |
| FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, |
| FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, |
| |
| @@ -182,11 +182,11 @@ enum { |
| /* IPSR5 */ |
| FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, |
| FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, |
| - FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, |
| - FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX, |
| + FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, |
| + FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX, |
| FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, |
| - FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, |
| - FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B, |
| + FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, |
| + FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B, |
| FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, |
| FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, |
| FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, |
| @@ -210,10 +210,10 @@ enum { |
| FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, |
| FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, |
| FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, |
| - FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, |
| - FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER, |
| + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, |
| + FN_I2C2_SCL_E, FN_ETH_RX_ER, FN_RMII_RX_ER, |
| FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, |
| - FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0, |
| + FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, FN_RMII_RXD0, |
| FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, |
| FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, |
| FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, |
| @@ -269,11 +269,11 @@ enum { |
| FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, |
| FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, |
| FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, |
| - FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, |
| - FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, |
| + FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, |
| + FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, |
| FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, |
| - FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, |
| - FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, |
| + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, |
| + FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, |
| FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD, |
| FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, |
| FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, |
| @@ -283,12 +283,12 @@ enum { |
| FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, |
| FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, |
| FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, |
| - FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B, |
| + FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, |
| FN_VI3_CLK_B, |
| |
| /* IPSR10 */ |
| FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, |
| - FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, |
| + FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, |
| FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, |
| FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, |
| FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, |
| @@ -322,9 +322,9 @@ enum { |
| FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, |
| FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, |
| FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, |
| - FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, |
| - FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, |
| - FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN, |
| + FN_RDS_DATA_E, FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, |
| + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, |
| + FN_I2C2_SDA_B, FN_MLB_DAT, FN_SPV_EVEN, |
| FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, |
| FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B, |
| FN_MOUT0, |
| @@ -378,12 +378,12 @@ enum { |
| FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, |
| FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, |
| FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, |
| - FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C, |
| - FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, |
| + FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C, |
| + FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, |
| FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, |
| FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, |
| FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, |
| - FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, |
| + FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, |
| FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, |
| FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, |
| FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, |
| @@ -398,9 +398,9 @@ enum { |
| /* IPSR15 */ |
| FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7, |
| FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, |
| - FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS, |
| + FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, |
| FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17, |
| - FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0, |
| + FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, |
| FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, |
| FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, |
| FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, |
| @@ -491,9 +491,9 @@ enum { |
| VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, |
| SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, |
| VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, |
| - SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, |
| - SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK, |
| - VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK, |
| + IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, |
| + I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, |
| + VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, |
| D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK, |
| VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, |
| |
| @@ -558,11 +558,11 @@ enum { |
| EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, |
| VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, |
| EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, |
| - VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK, |
| - INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, |
| + VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK, |
| + INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, |
| MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, |
| - VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK, |
| - SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, |
| + VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK, |
| + I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, |
| CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, |
| CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, |
| VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, |
| @@ -585,10 +585,10 @@ enum { |
| MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, |
| SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, |
| ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, |
| - TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK, |
| - SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, |
| + TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, |
| + I2C2_SCL_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, |
| STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, |
| - SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, |
| + IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, |
| STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, |
| SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, |
| RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, |
| @@ -641,11 +641,11 @@ enum { |
| SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, |
| SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, |
| SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, |
| - GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK, |
| - SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, |
| + GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK, |
| + I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, |
| MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, |
| - GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK, |
| - SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, |
| + GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, |
| + I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, |
| AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK, |
| AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK, |
| SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK, |
| @@ -655,11 +655,11 @@ enum { |
| SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK, |
| SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, |
| TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, |
| - SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK, |
| + IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, |
| VI3_CLK_B_MARK, |
| |
| SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, |
| - GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK, |
| + GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK, |
| SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, |
| VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, |
| VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, |
| @@ -692,9 +692,9 @@ enum { |
| VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, |
| MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, |
| RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK, |
| - RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK, |
| - MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK, |
| - SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, |
| + RDS_DATA_E_MARK, MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, |
| + MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, |
| + I2C2_SDA_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, |
| SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, |
| RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK, |
| MOUT0_MARK, |
| @@ -745,12 +745,12 @@ enum { |
| AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, |
| DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, |
| REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, |
| - MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK, |
| - SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, |
| + MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK, |
| + I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, |
| DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, |
| TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, |
| HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, |
| - LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK, |
| + LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, |
| SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK, |
| MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, |
| SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, |
| @@ -764,9 +764,9 @@ enum { |
| |
| SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, |
| LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, |
| - DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK, |
| + DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, |
| SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK, |
| - SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK, |
| + IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, |
| DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, |
| DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, |
| LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, |
| @@ -835,18 +835,18 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), |
| PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), |
| PINMUX_IPSR_DATA(IP0_22_20, D6), |
| - PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2), |
| + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), |
| PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), |
| PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), |
| PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), |
| - PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2), |
| + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), |
| PINMUX_IPSR_DATA(IP0_26_23, D7), |
| PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), |
| - PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2), |
| + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), |
| PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), |
| PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), |
| PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), |
| - PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2), |
| + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), |
| PINMUX_IPSR_DATA(IP0_30_27, D8), |
| PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), |
| PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), |
| @@ -1063,10 +1063,10 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), |
| PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), |
| PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), |
| - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0), |
| + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0), |
| PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), |
| PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), |
| - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0), |
| + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0), |
| PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), |
| PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), |
| PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), |
| @@ -1074,9 +1074,9 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), |
| PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), |
| PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), |
| - PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0), |
| + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0), |
| PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), |
| - PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0), |
| + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0), |
| PINMUX_IPSR_DATA(IP5_12_10, BS_N), |
| PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), |
| PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), |
| @@ -1152,15 +1152,15 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), |
| PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), |
| PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), |
| - PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4), |
| - PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4), |
| + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), |
| + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), |
| PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), |
| PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER), |
| PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), |
| PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), |
| PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), |
| - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4), |
| - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4), |
| + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), |
| + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), |
| PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), |
| PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0), |
| PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), |
| @@ -1315,8 +1315,8 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), |
| PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), |
| PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), |
| - PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1), |
| - PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1), |
| + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), |
| + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), |
| PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), |
| PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), |
| PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), |
| @@ -1324,8 +1324,8 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), |
| PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), |
| PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), |
| - PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1), |
| - PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1), |
| + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), |
| + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), |
| PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), |
| PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), |
| PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), |
| @@ -1356,8 +1356,8 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), |
| PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), |
| PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), |
| - PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3), |
| - PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3), |
| + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), |
| + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), |
| PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), |
| PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), |
| |
| @@ -1367,8 +1367,8 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), |
| PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), |
| PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), |
| - PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3), |
| - PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3), |
| + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), |
| + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), |
| PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), |
| PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), |
| PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), |
| @@ -1477,13 +1477,13 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), |
| PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4), |
| PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), |
| - PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1), |
| - PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1), |
| + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), |
| + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), |
| PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), |
| PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), |
| PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), |
| - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1), |
| - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1), |
| + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), |
| + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), |
| PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), |
| PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN), |
| PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), |
| @@ -1633,8 +1633,8 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), |
| PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), |
| PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), |
| - PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2), |
| - PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2), |
| + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), |
| + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), |
| PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), |
| PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), |
| PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), |
| @@ -1652,8 +1652,8 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), |
| PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0), |
| PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0), |
| - PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2), |
| - PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2), |
| + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), |
| + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), |
| PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), |
| PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), |
| PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS), |
| @@ -1695,20 +1695,20 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), |
| PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), |
| PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), |
| - PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0), |
| - PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0), |
| + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0), |
| + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0), |
| PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), |
| PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), |
| PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), |
| PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), |
| - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0), |
| - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0), |
| + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0), |
| + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0), |
| PINMUX_IPSR_DATA(IP15_11_9, HSCK0), |
| PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), |
| PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), |
| PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), |
| PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0), |
| - PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0), |
| + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, I2C2_SDA, SEL_I2C2_0), |
| PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), |
| PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), |
| PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), |
| @@ -3204,12 +3204,12 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| /* IP0_26_23 [4] */ |
| - FN_D7, FN_AD_DI_B, FN_SDA2_C, |
| - FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, |
| + FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, |
| + FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| /* IP0_22_20 [3] */ |
| - FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, |
| - FN_SCL2_CIS_C, 0, 0, |
| + FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, |
| + FN_I2C2_SCL_C, 0, 0, |
| /* IP0_19_16 [4] */ |
| FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, |
| FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, |
| @@ -3391,12 +3391,12 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| 0, 0, |
| /* IP5_9_6 [4] */ |
| FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, |
| - FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, |
| - FN_SDA1_CIS, 0, 0, 0, 0, 0, 0, |
| + FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, |
| + FN_I2C1_SDA, 0, 0, 0, 0, 0, 0, |
| /* IP5_5_3 [3] */ |
| FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, |
| - FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, |
| - FN_INTC_EN0_N, FN_SCL1_CIS, |
| + FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, |
| + FN_INTC_EN0_N, FN_I2C1_SCL, |
| /* IP5_2_0 [3] */ |
| FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, |
| FN_VI2_R3, 0, 0, } |
| @@ -3417,11 +3417,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, |
| /* IP6_19_17 [3] */ |
| FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, |
| - FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0, |
| + FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, |
| /* IP6_16_14 [3] */ |
| FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, |
| - FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, |
| - FN_SCL2_CIS_E, 0, |
| + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, |
| + FN_I2C2_SCL_E, 0, |
| /* IP6_13_11 [3] */ |
| FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, |
| FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, |
| @@ -3520,7 +3520,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { |
| /* IP9_31_28 [4] */ |
| FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, |
| - FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D, |
| + FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, |
| FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, |
| /* IP9_27_26 [2] */ |
| FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B, |
| @@ -3536,12 +3536,12 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0, |
| /* IP9_15_12 [4] */ |
| FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, |
| - FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, |
| - FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, |
| + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, |
| + FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, |
| /* IP9_11_8 [4] */ |
| FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, |
| - FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, |
| - FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, |
| + FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, |
| + FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, |
| /* IP9_7_6 [2] */ |
| FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, |
| /* IP9_5_4 [2] */ |
| @@ -3587,7 +3587,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| FN_VI3_DATA0_B, 0, |
| /* IP10_3_0 [4] */ |
| FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, |
| - FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, |
| + FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, |
| FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } |
| }, |
| { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, |
| @@ -3598,10 +3598,10 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, |
| FN_RDS_CLK_B, 0, 0, |
| /* IP11_26_24 [3] */ |
| - FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B, |
| + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, |
| 0, 0, 0, |
| /* IP11_23_22 [2] */ |
| - FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0, |
| + FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0, |
| /* IP11_21_18 [4] */ |
| FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, |
| FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, |
| @@ -3724,7 +3724,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, |
| /* IP14_15_12 [4] */ |
| FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, |
| - FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, |
| + FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, |
| 0, 0, 0, 0, 0, 0, 0, |
| /* IP14_11_9 [3] */ |
| FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, |
| @@ -3734,7 +3734,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| 0, 0, 0, |
| /* IP14_5_3 [3] */ |
| FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, |
| - FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C, |
| + FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C, |
| /* IP14_2_0 [3] */ |
| FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, |
| FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, |
| @@ -3767,10 +3767,10 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| 0, 0, 0, |
| /* IP15_8_6 [3] */ |
| FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17, |
| - FN_SDA2, FN_SDA2_CIS, 0, |
| + FN_IIC2_SDA, FN_I2C2_SDA, 0, |
| /* IP15_5_3 [3] */ |
| FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16, |
| - FN_SCL2, FN_SCL2_CIS, 0, |
| + FN_IIC2_SCL, FN_I2C2_SCL, 0, |
| /* IP15_2_0 [3] */ |
| FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7, |
| FN_LCDOUT15, FN_SCIF_CLK_B, 0, } |
| -- |
| 1.8.4.3.gca3854a |
| |
