| From 5c71f2209ad503afc2c822c9d99b2a1168171afc Mon Sep 17 00:00:00 2001 |
| From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> |
| Date: Fri, 24 May 2013 17:28:17 +0900 |
| Subject: sh-pfc: r8a7790: Remove trailing '_TANS' string from RTS/CTS pins |
| |
| The RTS/CTS pins have been renamed in the datasheet, rename them here as |
| well. |
| |
| Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> |
| Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| (cherry picked from commit bcec7475d84c16c62d5310da96d1e34b9edc750a) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 20 ++++++++++---------- |
| 1 file changed, 10 insertions(+), 10 deletions(-) |
| |
| diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| index 3ddebc6b..55827243 100644 |
| --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| @@ -384,14 +384,14 @@ enum { |
| FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, |
| FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, |
| FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, |
| - FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, |
| + FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, |
| FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, |
| FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, |
| FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, |
| FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, |
| FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, |
| FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, |
| - FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, |
| + FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, |
| FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, |
| FN_HRTS0_N_C, |
| |
| @@ -751,14 +751,14 @@ enum { |
| TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, |
| HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, |
| LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, |
| - SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK, |
| + SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK, |
| MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, |
| SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, |
| DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, |
| SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, |
| LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, |
| CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, |
| - SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK, |
| + SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK, |
| MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, |
| HRTS0_N_C_MARK, |
| |
| @@ -1656,7 +1656,7 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), |
| PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), |
| PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), |
| - PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS), |
| + PINMUX_IPSR_DATA(IP14_18_16, RTS0_N), |
| PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), |
| PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), |
| PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), |
| @@ -1679,7 +1679,7 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_DATA(IP14_27_25, QCLK), |
| PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), |
| PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), |
| - PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS), |
| + PINMUX_IPSR_DATA(IP14_30_28, RTS1_N), |
| PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), |
| PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), |
| PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), |
| @@ -1849,7 +1849,7 @@ static const unsigned int scif0_ctrl_pins[] = { |
| RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), |
| }; |
| static const unsigned int scif0_ctrl_mux[] = { |
| - RTS0_N_TANS_MARK, CTS0_N_MARK, |
| + RTS0_N_MARK, CTS0_N_MARK, |
| }; |
| static const unsigned int scif0_data_b_pins[] = { |
| /* RX, TX */ |
| @@ -1878,7 +1878,7 @@ static const unsigned int scif1_ctrl_pins[] = { |
| RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), |
| }; |
| static const unsigned int scif1_ctrl_mux[] = { |
| - RTS1_N_TANS_MARK, CTS1_N_MARK, |
| + RTS1_N_MARK, CTS1_N_MARK, |
| }; |
| static const unsigned int scif1_data_b_pins[] = { |
| /* RX, TX */ |
| @@ -3707,7 +3707,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| /* IP14_30 [1] */ |
| 0, 0, |
| /* IP14_30_28 [3] */ |
| - FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, |
| + FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, |
| FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, |
| FN_HRTS0_N_C, 0, |
| /* IP14_27_25 [3] */ |
| @@ -3720,7 +3720,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, |
| FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, |
| /* IP14_18_16 [3] */ |
| - FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, |
| + FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, |
| FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, |
| /* IP14_15_12 [4] */ |
| FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, |
| -- |
| 1.8.4.3.gca3854a |
| |
