| From 56d947d068e57efc226bdaf981e6e1909cf1c90b Mon Sep 17 00:00:00 2001 |
| From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> |
| Date: Fri, 24 May 2013 16:56:54 +0900 |
| Subject: sh-pfc: r8a7790: Add SCIF2 pins configuration support |
| |
| Update the pinmux configuration tables to support the SCIF2 pins |
| (TX2/TX2_B, RX2/RX2_B, SCK2). |
| |
| Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> |
| Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| (cherry picked from commit 1ddb66cd6f337e3df5d51d0d3cdfd4507d9199c3) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 40 +++++++++++++++++++++--------------- |
| 1 file changed, 23 insertions(+), 17 deletions(-) |
| |
| diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| index 1ae1dc75..344be5e3 100644 |
| --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| @@ -141,9 +141,9 @@ enum { |
| FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, |
| FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, |
| FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, |
| - FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B, |
| + FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, |
| FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, |
| - FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B, |
| + FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, |
| FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, |
| FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, |
| |
| @@ -395,10 +395,10 @@ enum { |
| FN_HRTS0_N_C, |
| |
| /* IPSR15 */ |
| - FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7, |
| + FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, |
| FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, |
| - FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, |
| - FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17, |
| + FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, |
| + FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, |
| FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, |
| FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, |
| FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, |
| @@ -450,6 +450,7 @@ enum { |
| FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, |
| FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, |
| FN_SEL_CAN1_0, FN_SEL_CAN1_1, |
| + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, |
| FN_SEL_ADI_0, FN_SEL_ADI_1, |
| FN_SEL_SSP_0, FN_SEL_SSP_1, |
| FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, |
| @@ -516,9 +517,9 @@ enum { |
| A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, |
| SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, |
| A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, |
| - VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK, |
| + VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK, |
| A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, |
| - VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK, |
| + VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK, |
| A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, |
| VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, |
| |
| @@ -758,10 +759,10 @@ enum { |
| MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, |
| HRTS0_N_C_MARK, |
| |
| - SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, |
| + SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, |
| LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, |
| - DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, |
| - SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK, |
| + TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, |
| + SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK, |
| IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, |
| DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, |
| DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, |
| @@ -924,6 +925,7 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), |
| PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), |
| PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), |
| + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1), |
| PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), |
| PINMUX_IPSR_DATA(IP2_25_22, A9), |
| PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), |
| @@ -931,6 +933,7 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), |
| PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), |
| PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), |
| + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1), |
| PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), |
| PINMUX_IPSR_DATA(IP2_28_26, A10), |
| PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), |
| @@ -1639,18 +1642,21 @@ static const u16 pinmux_data[] = { |
| |
| PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), |
| PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), |
| + PINMUX_IPSR_DATA(IP15_2_0, SCK2), |
| PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), |
| PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), |
| PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), |
| PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0), |
| PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), |
| PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), |
| + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0), |
| PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), |
| PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), |
| PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0), |
| PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0), |
| PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), |
| PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), |
| + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0), |
| PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), |
| PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), |
| PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0), |
| @@ -3229,11 +3235,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, |
| /* IP2_25_22 [4] */ |
| FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, |
| - FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B, |
| + FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, |
| 0, 0, 0, 0, 0, 0, 0, 0, |
| /* IP2_21_18 [4] */ |
| FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, |
| - FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B, |
| + FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, |
| 0, 0, 0, 0, 0, 0, 0, 0, |
| /* IP2_17_15 [3] */ |
| FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, |
| @@ -3713,13 +3719,13 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, |
| 0, 0, 0, |
| /* IP15_8_6 [3] */ |
| - FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17, |
| + FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, |
| FN_IIC2_SDA, FN_I2C2_SDA, 0, |
| /* IP15_5_3 [3] */ |
| - FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16, |
| + FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16, |
| FN_IIC2_SCL, FN_I2C2_SCL, 0, |
| /* IP15_2_0 [3] */ |
| - FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7, |
| + FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, |
| FN_LCDOUT15, FN_SCIF_CLK_B, 0, } |
| }, |
| { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, |
| @@ -3824,8 +3830,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { |
| FN_SEL_CAN1_0, FN_SEL_CAN1_1, |
| /* RESERVED [2] */ |
| 0, 0, 0, 0, |
| - /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */ |
| - 0, 0, |
| + /* SEL_SCIF2 [1] */ |
| + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, |
| /* SEL_ADI [1] */ |
| FN_SEL_ADI_0, FN_SEL_ADI_1, |
| /* SEL_SSP [1] */ |
| -- |
| 1.8.4.3.gca3854a |
| |
