| From 58b9dde799cd3f3c6ccecb901611efdc50566ab0 Mon Sep 17 00:00:00 2001 |
| From: Kunihito Higashiyama <kunihito.higashiyama.ur@renesas.com> |
| Date: Fri, 28 Jun 2013 09:36:09 +0900 |
| Subject: sh-pfc: r8a7790: Add MSIOF pin groups and functions |
| |
| Signed-off-by: Kunihito Higashiyama <kunihito.higashiyama.ur@renesas.com> |
| Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> |
| Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| (cherry picked from commit 4f47cc5e307db4b7219012878cb3f7a65eaa2f7c) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 236 +++++++++++++++++++++++++++++++++++ |
| 1 file changed, 236 insertions(+) |
| |
| diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| index e0337832..8e61ba0c 100644 |
| --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c |
| @@ -1989,6 +1989,178 @@ static const unsigned int mmc1_ctrl_pins[] = { |
| static const unsigned int mmc1_ctrl_mux[] = { |
| MMC1_CLK_MARK, MMC1_CMD_MARK, |
| }; |
| +/* - MSIOF0 ----------------------------------------------------------------- */ |
| +static const unsigned int msiof0_clk_pins[] = { |
| + /* SCK */ |
| + RCAR_GP_PIN(5, 12), |
| +}; |
| +static const unsigned int msiof0_clk_mux[] = { |
| + MSIOF0_SCK_MARK, |
| +}; |
| +static const unsigned int msiof0_sync_pins[] = { |
| + /* SYNC */ |
| + RCAR_GP_PIN(5, 13), |
| +}; |
| +static const unsigned int msiof0_sync_mux[] = { |
| + MSIOF0_SYNC_MARK, |
| +}; |
| +static const unsigned int msiof0_ss1_pins[] = { |
| + /* SS1 */ |
| + RCAR_GP_PIN(5, 14), |
| +}; |
| +static const unsigned int msiof0_ss1_mux[] = { |
| + MSIOF0_SS1_MARK, |
| +}; |
| +static const unsigned int msiof0_ss2_pins[] = { |
| + /* SS2 */ |
| + RCAR_GP_PIN(5, 16), |
| +}; |
| +static const unsigned int msiof0_ss2_mux[] = { |
| + MSIOF0_SS2_MARK, |
| +}; |
| +static const unsigned int msiof0_rx_pins[] = { |
| + /* RXD */ |
| + RCAR_GP_PIN(5, 17), |
| +}; |
| +static const unsigned int msiof0_rx_mux[] = { |
| + MSIOF0_RXD_MARK, |
| +}; |
| +static const unsigned int msiof0_tx_pins[] = { |
| + /* TXD */ |
| + RCAR_GP_PIN(5, 15), |
| +}; |
| +static const unsigned int msiof0_tx_mux[] = { |
| + MSIOF0_TXD_MARK, |
| +}; |
| +/* - MSIOF1 ----------------------------------------------------------------- */ |
| +static const unsigned int msiof1_clk_pins[] = { |
| + /* SCK */ |
| + RCAR_GP_PIN(4, 8), |
| +}; |
| +static const unsigned int msiof1_clk_mux[] = { |
| + MSIOF1_SCK_MARK, |
| +}; |
| +static const unsigned int msiof1_sync_pins[] = { |
| + /* SYNC */ |
| + RCAR_GP_PIN(4, 9), |
| +}; |
| +static const unsigned int msiof1_sync_mux[] = { |
| + MSIOF1_SYNC_MARK, |
| +}; |
| +static const unsigned int msiof1_ss1_pins[] = { |
| + /* SS1 */ |
| + RCAR_GP_PIN(4, 10), |
| +}; |
| +static const unsigned int msiof1_ss1_mux[] = { |
| + MSIOF1_SS1_MARK, |
| +}; |
| +static const unsigned int msiof1_ss2_pins[] = { |
| + /* SS2 */ |
| + RCAR_GP_PIN(4, 11), |
| +}; |
| +static const unsigned int msiof1_ss2_mux[] = { |
| + MSIOF1_SS2_MARK, |
| +}; |
| +static const unsigned int msiof1_rx_pins[] = { |
| + /* RXD */ |
| + RCAR_GP_PIN(4, 13), |
| +}; |
| +static const unsigned int msiof1_rx_mux[] = { |
| + MSIOF1_RXD_MARK, |
| +}; |
| +static const unsigned int msiof1_tx_pins[] = { |
| + /* TXD */ |
| + RCAR_GP_PIN(4, 12), |
| +}; |
| +static const unsigned int msiof1_tx_mux[] = { |
| + MSIOF1_TXD_MARK, |
| +}; |
| +/* - MSIOF2 ----------------------------------------------------------------- */ |
| +static const unsigned int msiof2_clk_pins[] = { |
| + /* SCK */ |
| + RCAR_GP_PIN(0, 27), |
| +}; |
| +static const unsigned int msiof2_clk_mux[] = { |
| + MSIOF2_SCK_MARK, |
| +}; |
| +static const unsigned int msiof2_sync_pins[] = { |
| + /* SYNC */ |
| + RCAR_GP_PIN(0, 26), |
| +}; |
| +static const unsigned int msiof2_sync_mux[] = { |
| + MSIOF2_SYNC_MARK, |
| +}; |
| +static const unsigned int msiof2_ss1_pins[] = { |
| + /* SS1 */ |
| + RCAR_GP_PIN(0, 30), |
| +}; |
| +static const unsigned int msiof2_ss1_mux[] = { |
| + MSIOF2_SS1_MARK, |
| +}; |
| +static const unsigned int msiof2_ss2_pins[] = { |
| + /* SS2 */ |
| + RCAR_GP_PIN(0, 31), |
| +}; |
| +static const unsigned int msiof2_ss2_mux[] = { |
| + MSIOF2_SS2_MARK, |
| +}; |
| +static const unsigned int msiof2_rx_pins[] = { |
| + /* RXD */ |
| + RCAR_GP_PIN(0, 29), |
| +}; |
| +static const unsigned int msiof2_rx_mux[] = { |
| + MSIOF2_RXD_MARK, |
| +}; |
| +static const unsigned int msiof2_tx_pins[] = { |
| + /* TXD */ |
| + RCAR_GP_PIN(0, 28), |
| +}; |
| +static const unsigned int msiof2_tx_mux[] = { |
| + MSIOF2_TXD_MARK, |
| +}; |
| +/* - MSIOF3 ----------------------------------------------------------------- */ |
| +static const unsigned int msiof3_clk_pins[] = { |
| + /* SCK */ |
| + RCAR_GP_PIN(5, 4), |
| +}; |
| +static const unsigned int msiof3_clk_mux[] = { |
| + MSIOF3_SCK_MARK, |
| +}; |
| +static const unsigned int msiof3_sync_pins[] = { |
| + /* SYNC */ |
| + RCAR_GP_PIN(4, 30), |
| +}; |
| +static const unsigned int msiof3_sync_mux[] = { |
| + MSIOF3_SYNC_MARK, |
| +}; |
| +static const unsigned int msiof3_ss1_pins[] = { |
| + /* SS1 */ |
| + RCAR_GP_PIN(4, 31), |
| +}; |
| +static const unsigned int msiof3_ss1_mux[] = { |
| + MSIOF3_SS1_MARK, |
| +}; |
| +static const unsigned int msiof3_ss2_pins[] = { |
| + /* SS2 */ |
| + RCAR_GP_PIN(4, 27), |
| +}; |
| +static const unsigned int msiof3_ss2_mux[] = { |
| + MSIOF3_SS2_MARK, |
| +}; |
| +static const unsigned int msiof3_rx_pins[] = { |
| + /* RXD */ |
| + RCAR_GP_PIN(5, 2), |
| +}; |
| +static const unsigned int msiof3_rx_mux[] = { |
| + MSIOF3_RXD_MARK, |
| +}; |
| +static const unsigned int msiof3_tx_pins[] = { |
| + /* TXD */ |
| + RCAR_GP_PIN(5, 3), |
| +}; |
| +static const unsigned int msiof3_tx_mux[] = { |
| + MSIOF3_TXD_MARK, |
| +}; |
| /* - SCIF0 ------------------------------------------------------------------ */ |
| static const unsigned int scif0_data_pins[] = { |
| /* RX, TX */ |
| @@ -2655,6 +2827,30 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { |
| SH_PFC_PIN_GROUP(mmc1_data4), |
| SH_PFC_PIN_GROUP(mmc1_data8), |
| SH_PFC_PIN_GROUP(mmc1_ctrl), |
| + SH_PFC_PIN_GROUP(msiof0_clk), |
| + SH_PFC_PIN_GROUP(msiof0_sync), |
| + SH_PFC_PIN_GROUP(msiof0_ss1), |
| + SH_PFC_PIN_GROUP(msiof0_ss2), |
| + SH_PFC_PIN_GROUP(msiof0_rx), |
| + SH_PFC_PIN_GROUP(msiof0_tx), |
| + SH_PFC_PIN_GROUP(msiof1_clk), |
| + SH_PFC_PIN_GROUP(msiof1_sync), |
| + SH_PFC_PIN_GROUP(msiof1_ss1), |
| + SH_PFC_PIN_GROUP(msiof1_ss2), |
| + SH_PFC_PIN_GROUP(msiof1_rx), |
| + SH_PFC_PIN_GROUP(msiof1_tx), |
| + SH_PFC_PIN_GROUP(msiof2_clk), |
| + SH_PFC_PIN_GROUP(msiof2_sync), |
| + SH_PFC_PIN_GROUP(msiof2_ss1), |
| + SH_PFC_PIN_GROUP(msiof2_ss2), |
| + SH_PFC_PIN_GROUP(msiof2_rx), |
| + SH_PFC_PIN_GROUP(msiof2_tx), |
| + SH_PFC_PIN_GROUP(msiof3_clk), |
| + SH_PFC_PIN_GROUP(msiof3_sync), |
| + SH_PFC_PIN_GROUP(msiof3_ss1), |
| + SH_PFC_PIN_GROUP(msiof3_ss2), |
| + SH_PFC_PIN_GROUP(msiof3_rx), |
| + SH_PFC_PIN_GROUP(msiof3_tx), |
| SH_PFC_PIN_GROUP(scif0_data), |
| SH_PFC_PIN_GROUP(scif0_clk), |
| SH_PFC_PIN_GROUP(scif0_ctrl), |
| @@ -2798,6 +2994,42 @@ static const char * const mmc1_groups[] = { |
| "mmc1_ctrl", |
| }; |
| |
| +static const char * const msiof0_groups[] = { |
| + "msiof0_clk", |
| + "msiof0_sync", |
| + "msiof0_ss1", |
| + "msiof0_ss2", |
| + "msiof0_rx", |
| + "msiof0_tx", |
| +}; |
| + |
| +static const char * const msiof1_groups[] = { |
| + "msiof1_clk", |
| + "msiof1_sync", |
| + "msiof1_ss1", |
| + "msiof1_ss2", |
| + "msiof1_rx", |
| + "msiof1_tx", |
| +}; |
| + |
| +static const char * const msiof2_groups[] = { |
| + "msiof2_clk", |
| + "msiof2_sync", |
| + "msiof2_ss1", |
| + "msiof2_ss2", |
| + "msiof2_rx", |
| + "msiof2_tx", |
| +}; |
| + |
| +static const char * const msiof3_groups[] = { |
| + "msiof3_clk", |
| + "msiof3_sync", |
| + "msiof3_ss1", |
| + "msiof3_ss2", |
| + "msiof3_rx", |
| + "msiof3_tx", |
| +}; |
| + |
| static const char * const scif0_groups[] = { |
| "scif0_data", |
| "scif0_clk", |
| @@ -2932,6 +3164,10 @@ static const struct sh_pfc_function pinmux_functions[] = { |
| SH_PFC_FUNCTION(intc), |
| SH_PFC_FUNCTION(mmc0), |
| SH_PFC_FUNCTION(mmc1), |
| + SH_PFC_FUNCTION(msiof0), |
| + SH_PFC_FUNCTION(msiof1), |
| + SH_PFC_FUNCTION(msiof2), |
| + SH_PFC_FUNCTION(msiof3), |
| SH_PFC_FUNCTION(scif0), |
| SH_PFC_FUNCTION(scif1), |
| SH_PFC_FUNCTION(scifa0), |
| -- |
| 1.8.4.3.gca3854a |
| |