| From 87b7edbaa34fc283e4e115cbf2f0b0a8d66a7b47 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Fri, 20 Jun 2014 14:37:38 +0200 |
| Subject: dmaengine: shdma: Add more register documentation |
| |
| Also add a few definitions that were missing. |
| |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 6b32fafee2bb5fcf0b3d3d04a9762d3a0212089e) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/sh/include/asm/dma-register.h | 36 +++++++++++++++++++----------------- |
| drivers/dma/sh/shdmac.c | 12 ++++++------ |
| include/linux/sh_dma.h | 24 +++++++++++++----------- |
| 3 files changed, 38 insertions(+), 34 deletions(-) |
| |
| diff --git a/arch/sh/include/asm/dma-register.h b/arch/sh/include/asm/dma-register.h |
| index 51cd78feacff..c757b47e6b64 100644 |
| --- a/arch/sh/include/asm/dma-register.h |
| +++ b/arch/sh/include/asm/dma-register.h |
| @@ -13,17 +13,17 @@ |
| #ifndef DMA_REGISTER_H |
| #define DMA_REGISTER_H |
| |
| -/* DMA register */ |
| -#define SAR 0x00 |
| -#define DAR 0x04 |
| -#define TCR 0x08 |
| -#define CHCR 0x0C |
| -#define DMAOR 0x40 |
| +/* DMA registers */ |
| +#define SAR 0x00 /* Source Address Register */ |
| +#define DAR 0x04 /* Destination Address Register */ |
| +#define TCR 0x08 /* Transfer Count Register */ |
| +#define CHCR 0x0C /* Channel Control Register */ |
| +#define DMAOR 0x40 /* DMA Operation Register */ |
| |
| /* DMAOR definitions */ |
| -#define DMAOR_AE 0x00000004 |
| +#define DMAOR_AE 0x00000004 /* Address Error Flag */ |
| #define DMAOR_NMIF 0x00000002 |
| -#define DMAOR_DME 0x00000001 |
| +#define DMAOR_DME 0x00000001 /* DMA Master Enable */ |
| |
| /* Definitions for the SuperH DMAC */ |
| #define REQ_L 0x00000000 |
| @@ -34,18 +34,20 @@ |
| #define ACK_W 0x00020000 |
| #define ACK_H 0x00000000 |
| #define ACK_L 0x00010000 |
| -#define DM_INC 0x00004000 |
| -#define DM_DEC 0x00008000 |
| -#define DM_FIX 0x0000c000 |
| -#define SM_INC 0x00001000 |
| -#define SM_DEC 0x00002000 |
| -#define SM_FIX 0x00003000 |
| +#define DM_INC 0x00004000 /* Destination addresses are incremented */ |
| +#define DM_DEC 0x00008000 /* Destination addresses are decremented */ |
| +#define DM_FIX 0x0000c000 /* Destination address is fixed */ |
| +#define SM_INC 0x00001000 /* Source addresses are incremented */ |
| +#define SM_DEC 0x00002000 /* Source addresses are decremented */ |
| +#define SM_FIX 0x00003000 /* Source address is fixed */ |
| #define RS_IN 0x00000200 |
| #define RS_OUT 0x00000300 |
| +#define RS_AUTO 0x00000400 /* Auto Request */ |
| +#define RS_ERS 0x00000800 /* DMA extended resource selector */ |
| #define TS_BLK 0x00000040 |
| #define TM_BUR 0x00000020 |
| -#define CHCR_DE 0x00000001 |
| -#define CHCR_TE 0x00000002 |
| -#define CHCR_IE 0x00000004 |
| +#define CHCR_DE 0x00000001 /* DMA Enable */ |
| +#define CHCR_TE 0x00000002 /* Transfer End Flag */ |
| +#define CHCR_IE 0x00000004 /* Interrupt Enable */ |
| |
| #endif |
| diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c |
| index 0d765c0e21ec..9acbba84759b 100644 |
| --- a/drivers/dma/sh/shdmac.c |
| +++ b/drivers/dma/sh/shdmac.c |
| @@ -37,12 +37,12 @@ |
| #include "../dmaengine.h" |
| #include "shdma.h" |
| |
| -/* DMA register */ |
| -#define SAR 0x00 |
| -#define DAR 0x04 |
| -#define TCR 0x08 |
| -#define CHCR 0x0C |
| -#define DMAOR 0x40 |
| +/* DMA registers */ |
| +#define SAR 0x00 /* Source Address Register */ |
| +#define DAR 0x04 /* Destination Address Register */ |
| +#define TCR 0x08 /* Transfer Count Register */ |
| +#define CHCR 0x0C /* Channel Control Register */ |
| +#define DMAOR 0x40 /* DMA Operation Register */ |
| |
| #define TEND 0x18 /* USB-DMAC */ |
| |
| diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h |
| index b7b43b82231e..56b97eed28a4 100644 |
| --- a/include/linux/sh_dma.h |
| +++ b/include/linux/sh_dma.h |
| @@ -95,19 +95,21 @@ struct sh_dmae_pdata { |
| }; |
| |
| /* DMAOR definitions */ |
| -#define DMAOR_AE 0x00000004 |
| +#define DMAOR_AE 0x00000004 /* Address Error Flag */ |
| #define DMAOR_NMIF 0x00000002 |
| -#define DMAOR_DME 0x00000001 |
| +#define DMAOR_DME 0x00000001 /* DMA Master Enable */ |
| |
| /* Definitions for the SuperH DMAC */ |
| -#define DM_INC 0x00004000 |
| -#define DM_DEC 0x00008000 |
| -#define DM_FIX 0x0000c000 |
| -#define SM_INC 0x00001000 |
| -#define SM_DEC 0x00002000 |
| -#define SM_FIX 0x00003000 |
| -#define CHCR_DE 0x00000001 |
| -#define CHCR_TE 0x00000002 |
| -#define CHCR_IE 0x00000004 |
| +#define DM_INC 0x00004000 /* Destination addresses are incremented */ |
| +#define DM_DEC 0x00008000 /* Destination addresses are decremented */ |
| +#define DM_FIX 0x0000c000 /* Destination address is fixed */ |
| +#define SM_INC 0x00001000 /* Source addresses are incremented */ |
| +#define SM_DEC 0x00002000 /* Source addresses are decremented */ |
| +#define SM_FIX 0x00003000 /* Source address is fixed */ |
| +#define RS_AUTO 0x00000400 /* Auto Request */ |
| +#define RS_ERS 0x00000800 /* DMA extended resource selector */ |
| +#define CHCR_DE 0x00000001 /* DMA Enable */ |
| +#define CHCR_TE 0x00000002 /* Transfer End Flag */ |
| +#define CHCR_IE 0x00000004 /* Interrupt Enable */ |
| |
| #endif |
| -- |
| 2.1.2 |
| |
