| From dc1a0f258a8d0fb18500483169f757f7cb23ee87 Mon Sep 17 00:00:00 2001 |
| From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Date: Fri, 16 Feb 2018 21:30:23 +0300 |
| Subject: [PATCH 0980/1795] arm64: dts: renesas: r8a77980: add [H]SCIF support |
| |
| Describe [H]SCIF ports in the R8A77980 device tree. |
| |
| Based on the original (and large) patch by Vladimir Barinov. |
| |
| Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> |
| Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 3601d98ceab56e3d04c9c5e029903bee0337cb94) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| --- |
| arch/arm64/boot/dts/renesas/r8a77980.dtsi | 151 ++++++++++++++++++++++ |
| 1 file changed, 151 insertions(+) |
| |
| diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi |
| index e5c7cf391334..eaa546f0a91f 100644 |
| --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi |
| +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi |
| @@ -56,6 +56,13 @@ |
| method = "smc"; |
| }; |
| |
| + /* External SCIF clock - to be overridden by boards that provide it */ |
| + scif_clk: scif { |
| + compatible = "fixed-clock"; |
| + #clock-cells = <0>; |
| + clock-frequency = <0>; |
| + }; |
| + |
| soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| @@ -85,6 +92,150 @@ |
| #power-domain-cells = <1>; |
| }; |
| |
| + hscif0: serial@e6540000 { |
| + compatible = "renesas,hscif-r8a77980", |
| + "renesas,rcar-gen3-hscif", |
| + "renesas,hscif"; |
| + reg = <0 0xe6540000 0 0x60>; |
| + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 520>, |
| + <&cpg CPG_CORE 19>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + dmas = <&dmac1 0x31>, <&dmac1 0x30>, |
| + <&dmac2 0x31>, <&dmac2 0x30>; |
| + dma-names = "tx", "rx", "tx", "rx"; |
| + power-domains = <&sysc 32>; |
| + resets = <&cpg 520>; |
| + status = "disabled"; |
| + }; |
| + |
| + hscif1: serial@e6550000 { |
| + compatible = "renesas,hscif-r8a77980", |
| + "renesas,rcar-gen3-hscif", |
| + "renesas,hscif"; |
| + reg = <0 0xe6550000 0 0x60>; |
| + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 519>, |
| + <&cpg CPG_CORE 19>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + dmas = <&dmac1 0x33>, <&dmac1 0x32>, |
| + <&dmac2 0x33>, <&dmac2 0x32>; |
| + dma-names = "tx", "rx", "tx", "rx"; |
| + power-domains = <&sysc 32>; |
| + resets = <&cpg 519>; |
| + status = "disabled"; |
| + }; |
| + |
| + hscif2: serial@e6560000 { |
| + compatible = "renesas,hscif-r8a77980", |
| + "renesas,rcar-gen3-hscif", |
| + "renesas,hscif"; |
| + reg = <0 0xe6560000 0 0x60>; |
| + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 518>, |
| + <&cpg CPG_CORE 19>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + dmas = <&dmac1 0x35>, <&dmac1 0x34>, |
| + <&dmac2 0x35>, <&dmac2 0x34>; |
| + dma-names = "tx", "rx", "tx", "rx"; |
| + power-domains = <&sysc 32>; |
| + resets = <&cpg 518>; |
| + status = "disabled"; |
| + }; |
| + |
| + hscif3: serial@e66a0000 { |
| + compatible = "renesas,hscif-r8a77980", |
| + "renesas,rcar-gen3-hscif", |
| + "renesas,hscif"; |
| + reg = <0 0xe66a0000 0 0x60>; |
| + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 517>, |
| + <&cpg CPG_CORE 19>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + dmas = <&dmac1 0x37>, <&dmac1 0x36>, |
| + <&dmac2 0x37>, <&dmac2 0x36>; |
| + dma-names = "tx", "rx", "tx", "rx"; |
| + power-domains = <&sysc 32>; |
| + resets = <&cpg 517>; |
| + status = "disabled"; |
| + }; |
| + |
| + scif0: serial@e6e60000 { |
| + compatible = "renesas,scif-r8a77980", |
| + "renesas,rcar-gen3-scif", |
| + "renesas,scif"; |
| + reg = <0 0xe6e60000 0 0x40>; |
| + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 207>, |
| + <&cpg CPG_CORE 19>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + dmas = <&dmac1 0x51>, <&dmac1 0x50>, |
| + <&dmac2 0x51>, <&dmac2 0x50>; |
| + dma-names = "tx", "rx", "tx", "rx"; |
| + power-domains = <&sysc 32>; |
| + resets = <&cpg 207>; |
| + status = "disabled"; |
| + }; |
| + |
| + scif1: serial@e6e68000 { |
| + compatible = "renesas,scif-r8a77980", |
| + "renesas,rcar-gen3-scif", |
| + "renesas,scif"; |
| + reg = <0 0xe6e68000 0 0x40>; |
| + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 206>, |
| + <&cpg CPG_CORE 19>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + dmas = <&dmac1 0x53>, <&dmac1 0x52>, |
| + <&dmac2 0x53>, <&dmac2 0x52>; |
| + dma-names = "tx", "rx", "tx", "rx"; |
| + power-domains = <&sysc 32>; |
| + resets = <&cpg 206>; |
| + status = "disabled"; |
| + }; |
| + |
| + scif3: serial@e6c50000 { |
| + compatible = "renesas,scif-r8a77980", |
| + "renesas,rcar-gen3-scif", |
| + "renesas,scif"; |
| + reg = <0 0xe6c50000 0 0x40>; |
| + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 204>, |
| + <&cpg CPG_CORE 19>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + dmas = <&dmac1 0x57>, <&dmac1 0x56>, |
| + <&dmac2 0x57>, <&dmac2 0x56>; |
| + dma-names = "tx", "rx", "tx", "rx"; |
| + power-domains = <&sysc 32>; |
| + resets = <&cpg 204>; |
| + status = "disabled"; |
| + }; |
| + |
| + scif4: serial@e6c40000 { |
| + compatible = "renesas,scif-r8a77980", |
| + "renesas,rcar-gen3-scif", |
| + "renesas,scif"; |
| + reg = <0 0xe6c40000 0 0x40>; |
| + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 203>, |
| + <&cpg CPG_CORE 19>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + dmas = <&dmac1 0x59>, <&dmac1 0x58>, |
| + <&dmac2 0x59>, <&dmac2 0x58>; |
| + dma-names = "tx", "rx", "tx", "rx"; |
| + power-domains = <&sysc 32>; |
| + resets = <&cpg 203>; |
| + status = "disabled"; |
| + }; |
| + |
| dmac1: dma-controller@e7300000 { |
| compatible = "renesas,dmac-r8a77980", |
| "renesas,rcar-dmac"; |
| -- |
| 2.19.0 |
| |