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| <div class="col-md-6 pull-left"><h1>AARCHMRS Schema <small>2.7.1</small></h1></div> |
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| <h1 id="27">2.7</h1> |
| <h2 id="highlights">Highlights</h2> |
| <h3 id="aarchmrs-5239-support-for-additional-combinations-of-readwrite-accesses-and-side-effects">AARCHMRS-5239: Support for additional combinations of read/write accesses and side effects</h3> |
| <p>Support has been added for the following shorthand read/write accesses:</p> |
| <ol> |
| <li><strong>RC/WS</strong> (W: sets all bits, R: clears all bits)</li> |
| <li><strong>RS/WC</strong> (W: clears all bits, R: sets all bits)</li> |
| <li><strong>RC/W1S</strong> (W: 1/0 sets/no effect on matching bit, R: clears all bits)</li> |
| <li><strong>RS/W1C</strong> (W: 1/0 clears/no effect on matching bit, R: sets all bits)</li> |
| <li><strong>RC/W0S</strong> (W: 1/0 no effect on/sets matching bit, R: clears all bits)</li> |
| <li><strong>RS/W0C</strong> (W: 1/0 no effect on/clears matching bit, R: sets all bits)</li> |
| <li><strong>ERROR/W</strong> (W: as-is, R: error)</li> |
| <li><strong>ERROR/W0C</strong> (W: clears all bits, R: error)</li> |
| <li><strong>ERROR/W0S</strong> (W: sets all bits, R: error)</li> |
| </ol> |
| <h3 id="aarchmrs-5227-update-asl1-implication-and-logical-equivalence-syntax">AARCHMRS-5227: Update ASL1 implication and logical equivalence syntax</h3> |
| <p>The syntax of the implication and logical equivalence has been updated in the BinaryOp schema |
| to align with the latest ASL reference documentation as the following:</p> |
| <ul> |
| <li>Implication: --> becomes ==></li> |
| <li>Biconditional: <-> becomes <=></li> |
| </ul> |
| <p>For more details refer to Chapter 3 of <a href="https://developer.arm.com/documentation/ddi0626/00bet0/?lang=en">ASLRef BET0</a>.</p> |
| <h3 id="aarchmrs-5226-change-astconcat-into-an-astbinaryop-operator">AARCHMRS-5226: Change AST.Concat into an AST.BinaryOp operator (<code>::</code>)</h3> |
| <p>In order to align more closely with the ASL Reference manual we have updated bit concatenation |
| to an AST.BinaryOp operator.</p> |
| <p>AST.Concat will remain in use when specifying mulit-bit field accesses of the form <code>REG.[F1,F2]</code> and is |
| planned for deprecation in a future version when a better model is made available.</p> |
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