commit b7b336b71aac5dbb02b53a82e7032524ba292713
author Marc Zyngier <marc.zyngier@arm.com> Mon Sep 17 20:27:32 2018 +0100
committer Marc Zyngier <marc.zyngier@arm.com> Tue Sep 18 19:38:20 2018 +0100
tree 68760e0fe4463d42843f12fdfed1619a4b201406
parent 173677c6812ce2b5748dfec2f9814f30c2cf01ce

arm64: KVM: NV: Reports GICv3 as being disabled for now

We currently don't support GICv3 for a guest hypervisor, so
let's report SRE as being disabled from EL3 (ICC_SRE_EL2 being
RAZ/WI).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

arch/arm64/kvm/sys_regs.c

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index d871dde..5110e3d 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1886,6 +1886,8 @@
 	{ SYS_DESC(SYS_RVBAR_EL2), access_rw, reset_val, RVBAR_EL2, 0 },
 	{ SYS_DESC(SYS_RMR_EL2), access_rw, reset_val, RMR_EL2, 0 },
 
+	{ SYS_DESC(SYS_ICC_SRE_EL2), trap_raz_wi },
+
 	{ SYS_DESC(SYS_CONTEXTIDR_EL2), access_rw, reset_val, CONTEXTIDR_EL2, 0 },
 	{ SYS_DESC(SYS_TPIDR_EL2), access_rw, reset_val, TPIDR_EL2, 0 },