| From 7ba06e10846d2641c7259519c9c90f05f30f776a Mon Sep 17 00:00:00 2001 |
| From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> |
| Date: Fri, 3 Feb 2017 14:18:39 -0800 |
| Subject: [PATCH] cpufreq: intel_pstate: Disable energy efficiency optimization |
| |
| commit 6e978b22efa1db9f6e71b24440b5f1d93e968ee3 upstream. |
| |
| Some Kabylake desktop processors may not reach max turbo when running in |
| HWP mode, even if running under sustained 100% utilization. |
| |
| This occurs when the HWP.EPP (Energy Performance Preference) is set to |
| "balance_power" (0x80) -- the default on most systems. |
| |
| It occurs because the platform BIOS may erroneously enable an |
| energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not |
| recommended to be enabled on this SKU. |
| |
| On the failing systems, this BIOS issue was not discovered when the |
| desktop motherboard was tested with Windows, because the BIOS also |
| neglects to provide the ACPI/CPPC table, that Windows requires to enable |
| HWP, and so Windows runs in legacy P-state mode, where this setting has |
| no effect. |
| |
| Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and |
| so it runs in HWP mode, exposing this incorrect BIOS configuration. |
| |
| There are several ways to address this problem. |
| |
| First, Linux can also run in legacy P-state mode on this system. |
| As intel_pstate is how Linux enables HWP, booting with |
| "intel_pstate=disable" |
| will run in acpi-cpufreq/ondemand legacy p-state mode. |
| |
| Or second, the "performance" governor can be used with intel_pstate, |
| which will modify HWP.EPP to 0. |
| |
| Or third, starting in 4.10, the |
| /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference |
| attribute in can be updated from "balance_power" to "performance". |
| |
| Or fourth, apply this patch, which fixes the erroneous setting of |
| MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default |
| configuration to function as designed. |
| |
| Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> |
| Reviewed-by: Len Brown <len.brown@intel.com> |
| Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ |
| Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> |
| |
| diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c |
| index 8c347f5c2562..263db70a8ffb 100644 |
| --- a/drivers/cpufreq/intel_pstate.c |
| +++ b/drivers/cpufreq/intel_pstate.c |
| @@ -812,6 +812,25 @@ static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
| wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
| } |
| |
| +#define MSR_IA32_POWER_CTL_BIT_EE 19 |
| + |
| +/* Disable energy efficiency optimization */ |
| +static void intel_pstate_disable_ee(int cpu) |
| +{ |
| + u64 power_ctl; |
| + int ret; |
| + |
| + ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl); |
| + if (ret) |
| + return; |
| + |
| + if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) { |
| + pr_info("Disabling energy efficiency optimization\n"); |
| + power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); |
| + wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl); |
| + } |
| +} |
| + |
| static int atom_get_min_pstate(void) |
| { |
| u64 value; |
| @@ -1391,6 +1410,11 @@ static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { |
| {} |
| }; |
| |
| +static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { |
| + ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params), |
| + {} |
| +}; |
| + |
| static int intel_pstate_init_cpu(unsigned int cpunum) |
| { |
| struct cpudata *cpu; |
| @@ -1406,6 +1430,12 @@ static int intel_pstate_init_cpu(unsigned int cpunum) |
| cpu->cpu = cpunum; |
| |
| if (hwp_active) { |
| + const struct x86_cpu_id *id; |
| + |
| + id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); |
| + if (id) |
| + intel_pstate_disable_ee(cpunum); |
| + |
| intel_pstate_hwp_enable(cpu); |
| pid_params.sample_rate_ms = 50; |
| pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; |
| -- |
| 2.12.0 |
| |