| From foo@baz Wed Feb 7 19:38:23 CST 2018 |
| From: David Woodhouse <dwmw@amazon.co.uk> |
| Date: Thu, 25 Jan 2018 16:14:13 +0000 |
| Subject: x86/pti: Do not enable PTI on CPUs which are not vulnerable to Meltdown |
| |
| From: David Woodhouse <dwmw@amazon.co.uk> |
| |
| (cherry picked from commit fec9434a12f38d3aeafeb75711b71d8a1fdef621) |
| |
| Also, for CPUs which don't speculate at all, don't report that they're |
| vulnerable to the Spectre variants either. |
| |
| Leave the cpu_no_meltdown[] match table with just X86_VENDOR_AMD in it |
| for now, even though that could be done with a simple comparison, on the |
| assumption that we'll have more to add. |
| |
| Based on suggestions from Dave Hansen and Alan Cox. |
| |
| Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> |
| Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
| Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| Reviewed-by: Borislav Petkov <bp@suse.de> |
| Acked-by: Dave Hansen <dave.hansen@intel.com> |
| Cc: gnomes@lxorguk.ukuu.org.uk |
| Cc: ak@linux.intel.com |
| Cc: ashok.raj@intel.com |
| Cc: karahmed@amazon.de |
| Cc: arjan@linux.intel.com |
| Cc: torvalds@linux-foundation.org |
| Cc: peterz@infradead.org |
| Cc: bp@alien8.de |
| Cc: pbonzini@redhat.com |
| Cc: tim.c.chen@linux.intel.com |
| Cc: gregkh@linux-foundation.org |
| Link: https://lkml.kernel.org/r/1516896855-7642-6-git-send-email-dwmw@amazon.co.uk |
| Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/x86/kernel/cpu/common.c | 48 ++++++++++++++++++++++++++++++++++++++----- |
| 1 file changed, 43 insertions(+), 5 deletions(-) |
| |
| --- a/arch/x86/kernel/cpu/common.c |
| +++ b/arch/x86/kernel/cpu/common.c |
| @@ -44,6 +44,8 @@ |
| #include <asm/pat.h> |
| #include <asm/microcode.h> |
| #include <asm/microcode_intel.h> |
| +#include <asm/intel-family.h> |
| +#include <asm/cpu_device_id.h> |
| |
| #ifdef CONFIG_X86_LOCAL_APIC |
| #include <asm/uv/uv.h> |
| @@ -838,6 +840,41 @@ static void identify_cpu_without_cpuid(s |
| #endif |
| } |
| |
| +static const __initdata struct x86_cpu_id cpu_no_speculation[] = { |
| + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, |
| + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, |
| + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, |
| + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, |
| + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, |
| + { X86_VENDOR_CENTAUR, 5 }, |
| + { X86_VENDOR_INTEL, 5 }, |
| + { X86_VENDOR_NSC, 5 }, |
| + { X86_VENDOR_ANY, 4 }, |
| + {} |
| +}; |
| + |
| +static const __initdata struct x86_cpu_id cpu_no_meltdown[] = { |
| + { X86_VENDOR_AMD }, |
| + {} |
| +}; |
| + |
| +static bool __init cpu_vulnerable_to_meltdown(struct cpuinfo_x86 *c) |
| +{ |
| + u64 ia32_cap = 0; |
| + |
| + if (x86_match_cpu(cpu_no_meltdown)) |
| + return false; |
| + |
| + if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) |
| + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); |
| + |
| + /* Rogue Data Cache Load? No! */ |
| + if (ia32_cap & ARCH_CAP_RDCL_NO) |
| + return false; |
| + |
| + return true; |
| +} |
| + |
| /* |
| * Do minimum CPU detection early. |
| * Fields really needed: vendor, cpuid_level, family, model, mask, |
| @@ -884,11 +921,12 @@ static void __init early_identify_cpu(st |
| |
| setup_force_cpu_cap(X86_FEATURE_ALWAYS); |
| |
| - if (c->x86_vendor != X86_VENDOR_AMD) |
| - setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); |
| - |
| - setup_force_cpu_bug(X86_BUG_SPECTRE_V1); |
| - setup_force_cpu_bug(X86_BUG_SPECTRE_V2); |
| + if (!x86_match_cpu(cpu_no_speculation)) { |
| + if (cpu_vulnerable_to_meltdown(c)) |
| + setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); |
| + setup_force_cpu_bug(X86_BUG_SPECTRE_V1); |
| + setup_force_cpu_bug(X86_BUG_SPECTRE_V2); |
| + } |
| |
| fpu__init_system(c); |
| |