| From e8fca0f1ba329770c76c93ec63f4472dd25c8e16 Mon Sep 17 00:00:00 2001 |
| From: Peter Zijlstra <peterz@infradead.org> |
| Date: Tue, 11 Apr 2017 10:10:28 +0200 |
| Subject: [PATCH] perf/x86: Avoid exposing wrong/stale data in |
| intel_pmu_lbr_read_32() |
| |
| commit f2200ac311302fcdca6556fd0c5127eab6c65a3e upstream. |
| |
| When the perf_branch_entry::{in_tx,abort,cycles} fields were added, |
| intel_pmu_lbr_read_32() wasn't updated to initialize them. |
| |
| Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> |
| Cc: Linus Torvalds <torvalds@linux-foundation.org> |
| Cc: Peter Zijlstra <peterz@infradead.org> |
| Cc: Thomas Gleixner <tglx@linutronix.de> |
| Cc: linux-kernel@vger.kernel.org |
| Cc: <stable@vger.kernel.org> |
| Fixes: 135c5612c460 ("perf/x86/intel: Support Haswell/v4 LBR format") |
| Signed-off-by: Ingo Molnar <mingo@kernel.org> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c |
| index 707d358e0dff..5d97308f1e11 100644 |
| --- a/arch/x86/events/intel/lbr.c |
| +++ b/arch/x86/events/intel/lbr.c |
| @@ -513,6 +513,9 @@ static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc) |
| cpuc->lbr_entries[i].to = msr_lastbranch.to; |
| cpuc->lbr_entries[i].mispred = 0; |
| cpuc->lbr_entries[i].predicted = 0; |
| + cpuc->lbr_entries[i].in_tx = 0; |
| + cpuc->lbr_entries[i].abort = 0; |
| + cpuc->lbr_entries[i].cycles = 0; |
| cpuc->lbr_entries[i].reserved = 0; |
| } |
| cpuc->lbr_stack.nr = i; |
| -- |
| 2.12.0 |
| |
