| From 86d7e53aa79e7814678745f1b1bbb2b8fc96e4b3 Mon Sep 17 00:00:00 2001 |
| From: Marian Mihailescu <mihailescu2m@gmail.com> |
| Date: Tue, 29 Oct 2019 11:20:25 +1030 |
| Subject: [PATCH] clk: samsung: exynos5420: Preserve CPU clocks configuration |
| during suspend/resume |
| |
| commit e21be0d1d7bd7f78a77613f6bcb6965e72b22fc1 upstream. |
| |
| Save and restore top PLL related configuration registers for big (APLL) |
| and LITTLE (KPLL) cores during suspend/resume cycle. So far, CPU clocks |
| were reset to default values after suspend/resume cycle and performance |
| after system resume was affected when performance governor has been selected. |
| |
| Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list") |
| Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com> |
| Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c |
| index 94b02273a941..4b55ef5e3b03 100644 |
| --- a/drivers/clk/samsung/clk-exynos5420.c |
| +++ b/drivers/clk/samsung/clk-exynos5420.c |
| @@ -164,6 +164,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = { |
| GATE_BUS_CPU, |
| GATE_SCLK_CPU, |
| CLKOUT_CMU_CPU, |
| + APLL_CON0, |
| + KPLL_CON0, |
| CPLL_CON0, |
| DPLL_CON0, |
| EPLL_CON0, |
| -- |
| 2.7.4 |
| |
