| From 5d01867748083932387147598d04c20189472b26 Mon Sep 17 00:00:00 2001 |
| From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> |
| Date: Tue, 24 Sep 2019 09:22:52 +0530 |
| Subject: [PATCH] powerpc/book3s64/radix: Rename CPU_FTR_P9_TLBIE_BUG feature |
| flag |
| |
| commit 09ce98cacd51fcd0fa0af2f79d1e1d3192f4cbb0 upstream. |
| |
| Rename the #define to indicate this is related to store vs tlbie |
| ordering issue. In the next patch, we will be adding another feature |
| flag that is used to handles ERAT flush vs tlbie ordering issue. |
| |
| Fixes: a5d4b5891c2f ("powerpc/mm: Fixup tlbie vs store ordering issue on POWER9") |
| Cc: stable@vger.kernel.org # v4.16+ |
| Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> |
| Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> |
| Link: https://lore.kernel.org/r/20190924035254.24612-2-aneesh.kumar@linux.ibm.com |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h |
| index d05f0c28e515..5885094a043f 100644 |
| --- a/arch/powerpc/include/asm/cputable.h |
| +++ b/arch/powerpc/include/asm/cputable.h |
| @@ -213,7 +213,7 @@ static inline void cpu_feature_keys_init(void) { } |
| #define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000) |
| #define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000) |
| #define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000) |
| -#define CPU_FTR_P9_TLBIE_BUG LONG_ASM_CONST(0x0000400000000000) |
| +#define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000) |
| #define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000) |
| |
| #ifndef __ASSEMBLY__ |
| @@ -461,7 +461,7 @@ static inline void cpu_feature_keys_init(void) { } |
| CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ |
| CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ |
| CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \ |
| - CPU_FTR_P9_TLBIE_BUG | CPU_FTR_P9_TIDR) |
| + CPU_FTR_P9_TLBIE_STQ_BUG | CPU_FTR_P9_TIDR) |
| #define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9 |
| #define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1) |
| #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \ |
| diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c |
| index eeaff2085120..4ddf2c7a7fb7 100644 |
| --- a/arch/powerpc/kernel/dt_cpu_ftrs.c |
| +++ b/arch/powerpc/kernel/dt_cpu_ftrs.c |
| @@ -705,14 +705,14 @@ static __init void update_tlbie_feature_flag(unsigned long pvr) |
| if ((pvr & 0xe000) == 0) { |
| /* Nimbus */ |
| if ((pvr & 0xfff) < 0x203) |
| - cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_BUG; |
| + cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG; |
| } else if ((pvr & 0xc000) == 0) { |
| /* Cumulus */ |
| if ((pvr & 0xfff) < 0x103) |
| - cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_BUG; |
| + cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG; |
| } else { |
| WARN_ONCE(1, "Unknown PVR"); |
| - cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_BUG; |
| + cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG; |
| } |
| } |
| } |
| diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c |
| index 63e0ce91e29d..7d89b1b10ea5 100644 |
| --- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c |
| +++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c |
| @@ -451,7 +451,7 @@ static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues, |
| "r" (rbvalues[i]), "r" (kvm->arch.lpid)); |
| } |
| |
| - if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) { |
| + if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) { |
| /* |
| * Need the extra ptesync to make sure we don't |
| * re-order the tlbie |
| diff --git a/arch/powerpc/mm/book3s64/hash_native.c b/arch/powerpc/mm/book3s64/hash_native.c |
| index 1322c59cb5dd..9a9ea227e7fa 100644 |
| --- a/arch/powerpc/mm/book3s64/hash_native.c |
| +++ b/arch/powerpc/mm/book3s64/hash_native.c |
| @@ -199,7 +199,7 @@ static inline unsigned long ___tlbie(unsigned long vpn, int psize, |
| |
| static inline void fixup_tlbie(unsigned long vpn, int psize, int apsize, int ssize) |
| { |
| - if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) { |
| + if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) { |
| /* Need the extra ptesync to ensure we don't reorder tlbie*/ |
| asm volatile("ptesync": : :"memory"); |
| ___tlbie(vpn, psize, apsize, ssize); |
| diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c b/arch/powerpc/mm/book3s64/radix_tlb.c |
| index d0cd5271a57c..781924e13ba5 100644 |
| --- a/arch/powerpc/mm/book3s64/radix_tlb.c |
| +++ b/arch/powerpc/mm/book3s64/radix_tlb.c |
| @@ -216,7 +216,7 @@ static inline void fixup_tlbie(void) |
| unsigned long pid = 0; |
| unsigned long va = ((1UL << 52) - 1); |
| |
| - if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) { |
| + if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) { |
| asm volatile("ptesync": : :"memory"); |
| __tlbie_va(va, pid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB); |
| } |
| @@ -226,7 +226,7 @@ static inline void fixup_tlbie_lpid(unsigned long lpid) |
| { |
| unsigned long va = ((1UL << 52) - 1); |
| |
| - if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) { |
| + if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) { |
| asm volatile("ptesync": : :"memory"); |
| __tlbie_lpid_va(va, lpid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB); |
| } |
| -- |
| 2.7.4 |
| |