| From e38decc2b96ccba28a93be58bcd08a451e57b99d Mon Sep 17 00:00:00 2001 |
| From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
| Date: Sun, 17 Nov 2019 16:41:54 +0100 |
| Subject: [PATCH] ARM: dts: meson8: fix the size of the PMU registers |
| |
| commit 46c9585ed4af688ff1be6d4e76d7ed2f04de4fba upstream. |
| |
| The PMU registers are at least 0x18 bytes wide. Meson8b already uses a |
| size of 0x18. The structure of the PMU registers on Meson8 and Meson8b |
| is similar but not identical. |
| |
| Meson8 and Meson8b have the following registers in common (starting at |
| AOBUS + 0xe0): |
| #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2) |
| #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2) |
| #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2) |
| #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2) |
| |
| Meson8b additionally has these three registers: |
| #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2) |
| #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2) |
| #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2) |
| |
| Thus we can assume that the register size of the PMU IP blocks is |
| identical on both SoCs (and Meson8 just contains some reserved registers |
| in that area) because the CEC registers start right after the PMU |
| (AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2). |
| |
| The upcoming power domain driver will need to read and write the |
| AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated |
| size is needed for that driver to work. |
| |
| Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores") |
| Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
| Signed-off-by: Kevin Hilman <khilman@baylibre.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi |
| index 40c11b6b217a..d8fb86925865 100644 |
| --- a/arch/arm/boot/dts/meson8.dtsi |
| +++ b/arch/arm/boot/dts/meson8.dtsi |
| @@ -271,7 +271,7 @@ |
| &aobus { |
| pmu: pmu@e0 { |
| compatible = "amlogic,meson8-pmu", "syscon"; |
| - reg = <0xe0 0x8>; |
| + reg = <0xe0 0x18>; |
| }; |
| |
| pinctrl_aobus: pinctrl@84 { |
| -- |
| 2.7.4 |
| |
