| From eb061b84c8267e426738845c97d45d19533bbce4 Mon Sep 17 00:00:00 2001 |
| From: Anson Huang <Anson.Huang@nxp.com> |
| Date: Fri, 11 Oct 2019 17:09:00 +0800 |
| Subject: [PATCH] clk: imx7ulp: Correct DDR clock mux options |
| |
| commit 2e2b928a04bd74ea410da72bd60e1c5b06398276 upstream. |
| |
| In the latest reference manual Rev.0,06/2019, the DDR clock mux |
| is extended to 2 bits, and the clock options are also changed, |
| correct them accordingly. |
| |
| Fixes: b1260067ac3d ("clk: imx: add imx7ulp clk driver") |
| Signed-off-by: Anson Huang <Anson.Huang@nxp.com> |
| Reviewed-by: Fabio Estevam <festevam@gmail.com> |
| Signed-off-by: Shawn Guo <shawnguo@kernel.org> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c |
| index 8adcf5c74687..65112d0e20dc 100644 |
| --- a/drivers/clk/imx/clk-imx7ulp.c |
| +++ b/drivers/clk/imx/clk-imx7ulp.c |
| @@ -25,7 +25,7 @@ static const char * const spll_sels[] = { "spll", "spll_pfd_sel", }; |
| static const char * const apll_pfd_sels[] = { "apll_pfd0", "apll_pfd1", "apll_pfd2", "apll_pfd3", }; |
| static const char * const apll_sels[] = { "apll", "apll_pfd_sel", }; |
| static const char * const scs_sels[] = { "dummy", "sosc", "sirc", "firc", "dummy", "apll_sel", "spll_sel", "dummy", }; |
| -static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", }; |
| +static const char * const ddr_sels[] = { "apll_pfd_sel", "dummy", "dummy", "dummy", }; |
| static const char * const nic_sels[] = { "firc", "ddr_clk", }; |
| static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", }; |
| static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", }; |
| @@ -106,7 +106,7 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) |
| clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels)); |
| clks[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_hw_mux2("hsrun_scs_sel", base + 0x1c, 24, 4, scs_sels, ARRAY_SIZE(scs_sels)); |
| clks[IMX7ULP_CLK_NIC_SEL] = imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels)); |
| - clks[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 1, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); |
| + clks[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); |
| |
| clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT); |
| clks[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT); |
| -- |
| 2.7.4 |
| |