| From 82ac645a93a6c205103a6e1bd51a5ecc4f9cfb87 Mon Sep 17 00:00:00 2001 |
| From: Chen-Yu Tsai <wens@csie.org> |
| Date: Wed, 18 Dec 2019 11:04:31 +0800 |
| Subject: [PATCH] clk: sunxi-ng: r40: Allow setting parent rate for external |
| clock outputs |
| |
| commit c7b305267eb77fe47498676e9337324c9653494c upstream. |
| |
| One of the uses of the external clock outputs is to provide a stable |
| 32768 Hz clock signal to WiFi and Bluetooth chips. On the R40, the RTC |
| has an internal RC oscillator that is muxed with the external crystal. |
| |
| Allow setting the parent rate for the external clock outputs so that |
| requests for 32768 Hz get passed to the RTC's clock driver to mux in |
| the external crystal if it isn't already muxed correctly. |
| |
| Fixes: cd030a78f7aa ("clk: sunxi-ng: support R40 SoC") |
| Fixes: 01a7ea763fc4 ("clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output") |
| Cc: <stable@kernel.org> |
| Signed-off-by: Chen-Yu Tsai <wens@csie.org> |
| Signed-off-by: Maxime Ripard <maxime@cerno.tech> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c |
| index 540f5f7454fc..8a5b8fcdcc2f 100644 |
| --- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c |
| +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c |
| @@ -761,7 +761,8 @@ static struct ccu_mp outa_clk = { |
| .reg = 0x1f0, |
| .features = CCU_FEATURE_FIXED_PREDIV, |
| .hw.init = CLK_HW_INIT_PARENTS("outa", out_parents, |
| - &ccu_mp_ops, 0), |
| + &ccu_mp_ops, |
| + CLK_SET_RATE_PARENT), |
| } |
| }; |
| |
| @@ -779,7 +780,8 @@ static struct ccu_mp outb_clk = { |
| .reg = 0x1f4, |
| .features = CCU_FEATURE_FIXED_PREDIV, |
| .hw.init = CLK_HW_INIT_PARENTS("outb", out_parents, |
| - &ccu_mp_ops, 0), |
| + &ccu_mp_ops, |
| + CLK_SET_RATE_PARENT), |
| } |
| }; |
| |
| -- |
| 2.7.4 |
| |