| From 2a1a8d09f8228231cd59f58c0a901f79b23d02a1 Mon Sep 17 00:00:00 2001 |
| From: Michael Grzeschik <m.grzeschik@pengutronix.de> |
| Date: Thu, 16 Jan 2020 14:16:31 +0100 |
| Subject: [PATCH] net: phy: dp83867: Set FORCE_LINK_GOOD to default after reset |
| |
| commit 86ffe920e669ec73035e84553e18edf17d16317c upstream. |
| |
| According to the Datasheet this bit should be 0 (Normal operation) in |
| default. With the FORCE_LINK_GOOD bit set, it is not possible to get a |
| link. This patch sets FORCE_LINK_GOOD to the default value after |
| resetting the phy. |
| |
| Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> |
| Reviewed-by: Andrew Lunn <andrew@lunn.ch> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c |
| index 97a1c4cf089c..6eaec42fec05 100644 |
| --- a/drivers/net/phy/dp83867.c |
| +++ b/drivers/net/phy/dp83867.c |
| @@ -67,6 +67,7 @@ |
| #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 |
| #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14) |
| #define DP83867_PHYCR_RESERVED_MASK BIT(11) |
| +#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) |
| |
| /* RGMIIDCTL bits */ |
| #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 |
| @@ -345,7 +346,12 @@ static int dp83867_phy_reset(struct phy_device *phydev) |
| |
| usleep_range(10, 20); |
| |
| - return 0; |
| + /* After reset FORCE_LINK_GOOD bit is set. Although the |
| + * default value should be unset. Disable FORCE_LINK_GOOD |
| + * for the phy to work properly. |
| + */ |
| + return phy_modify(phydev, MII_DP83867_PHYCTRL, |
| + DP83867_PHYCR_FORCE_LINK_GOOD, 0); |
| } |
| |
| static struct phy_driver dp83867_driver[] = { |
| -- |
| 2.7.4 |
| |
