| From 75c2879ec8a6acfd4988a43d11697b0dabcc36d3 Mon Sep 17 00:00:00 2001 |
| From: Jonas Karlman <jonas@kwiboo.se> |
| Date: Mon, 23 Dec 2019 08:49:19 +0000 |
| Subject: [PATCH] phy/rockchip: inno-hdmi: round clock rate down to closest |
| 1000 Hz |
| |
| commit 4f510aa10468954b1da4e94689c38ac6ea8d3627 upstream. |
| |
| Commit 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") |
| changed what rate clk_round_rate() is called with, an additional 999 Hz |
| added to the requsted mode clock. This has caused a regression on RK3328 |
| and presumably also on RK3228 because the inno-hdmi-phy clock requires an |
| exact match of the requested rate in the pre pll config table. |
| |
| When an exact match is not found the parent clock rate (24MHz) is returned |
| to the clk_round_rate() caller. This cause wrong pixel clock to be used and |
| result in no-signal when configuring a mode on RK3328. |
| |
| Fix this by rounding the rate down to closest 1000 Hz in round_rate func, |
| this allows an exact match to be found in pre pll config table. |
| |
| Fixes: 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") |
| Signed-off-by: Jonas Karlman <jonas@kwiboo.se> |
| Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c |
| index b10a84cab4a7..93290d0f1e7e 100644 |
| --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c |
| +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c |
| @@ -603,6 +603,8 @@ static long inno_hdmi_phy_rk3228_clk_round_rate(struct clk_hw *hw, |
| { |
| const struct pre_pll_config *cfg = pre_pll_cfg_table; |
| |
| + rate = (rate / 1000) * 1000; |
| + |
| for (; cfg->pixclock != 0; cfg++) |
| if (cfg->pixclock == rate && !cfg->fracdiv) |
| break; |
| @@ -755,6 +757,8 @@ static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw, |
| { |
| const struct pre_pll_config *cfg = pre_pll_cfg_table; |
| |
| + rate = (rate / 1000) * 1000; |
| + |
| for (; cfg->pixclock != 0; cfg++) |
| if (cfg->pixclock == rate) |
| break; |
| -- |
| 2.7.4 |
| |