| From 4df1d20a5a2e0985d78f51171d67286524dd279f Mon Sep 17 00:00:00 2001 |
| From: Andre Przywara <andre.przywara@arm.com> |
| Date: Thu, 21 Nov 2019 01:18:35 +0000 |
| Subject: [PATCH] arm: dts: allwinner: H3: Add PMU node |
| |
| commit 0388a110747bec0c9d9de995842bb2a03a26aae1 upstream. |
| |
| Add the Performance Monitoring Unit (PMU) device tree node to the H3 |
| .dtsi, which tells DT users which interrupts are triggered by PMU |
| overflow events on each core. The numbers come from the manual and have |
| been checked in U-Boot and with perf in Linux. |
| |
| Tested with perf record and taskset on an OrangePi Zero. |
| |
| Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
| Signed-off-by: Maxime Ripard <maxime@cerno.tech> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi |
| index e37c30e811d3..6056f206c9e3 100644 |
| --- a/arch/arm/boot/dts/sun8i-h3.dtsi |
| +++ b/arch/arm/boot/dts/sun8i-h3.dtsi |
| @@ -80,7 +80,7 @@ |
| #cooling-cells = <2>; |
| }; |
| |
| - cpu@1 { |
| + cpu1: cpu@1 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <1>; |
| @@ -90,7 +90,7 @@ |
| #cooling-cells = <2>; |
| }; |
| |
| - cpu@2 { |
| + cpu2: cpu@2 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <2>; |
| @@ -100,7 +100,7 @@ |
| #cooling-cells = <2>; |
| }; |
| |
| - cpu@3 { |
| + cpu3: cpu@3 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <3>; |
| @@ -111,6 +111,15 @@ |
| }; |
| }; |
| |
| + pmu { |
| + compatible = "arm,cortex-a7-pmu"; |
| + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| + }; |
| + |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| -- |
| 2.7.4 |
| |
