| From a65c0198029f54d7aedf873e6e12608094acbab8 Mon Sep 17 00:00:00 2001 |
| From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
| Date: Thu, 26 Dec 2019 20:12:23 +0100 |
| Subject: [PATCH] clk: meson: meson8b: make the CCF use the glitch-free mali |
| mux |
| |
| commit 8daeaea99caabe24a0929fac17977ebfb882fa86 upstream. |
| |
| The "mali_0" or "mali_1" clock trees should not be updated while the |
| clock is running. Enforce this by setting CLK_SET_RATE_GATE on the |
| "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" |
| tree when "mali_0" is currently active and vice versa, which is exactly |
| what the vendor driver does when updating the frequency of the mali |
| clock. |
| |
| This fixes a potential hang when changing the GPU frequency at runtime. |
| |
| Fixes: 74e1f2521f16ff ("clk: meson: meson8b: add the GPU clock tree") |
| Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
| Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c |
| index 62cd3a7f1f65..173ac8835de0 100644 |
| --- a/drivers/clk/meson/meson8b.c |
| +++ b/drivers/clk/meson/meson8b.c |
| @@ -1576,8 +1576,11 @@ static struct clk_regmap meson8b_hdmi_sys = { |
| |
| /* |
| * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) |
| - * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only |
| - * has mali_0 and no glitch-free mux. |
| + * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can |
| + * actually manage this glitch-free mux because it does top-to-bottom |
| + * updates the each clock tree and switches to the "inactive" one when |
| + * CLK_SET_RATE_GATE is set. |
| + * Meson8 only has mali_0 and no glitch-free mux. |
| */ |
| static const char * const meson8b_mali_0_1_parent_names[] = { |
| "xtal", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3", |
| @@ -1633,7 +1636,7 @@ static struct clk_regmap meson8b_mali_0 = { |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "mali_0_div" }, |
| .num_parents = 1, |
| - .flags = CLK_SET_RATE_PARENT, |
| + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| @@ -1684,7 +1687,7 @@ static struct clk_regmap meson8b_mali_1 = { |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "mali_1_div" }, |
| .num_parents = 1, |
| - .flags = CLK_SET_RATE_PARENT, |
| + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| -- |
| 2.7.4 |
| |