| From 71da2d273b86a3e246661451dda374a64396f340 Mon Sep 17 00:00:00 2001 |
| From: Grygorii Strashko <grygorii.strashko@ti.com> |
| Date: Sat, 21 Dec 2019 13:00:04 +0200 |
| Subject: [PATCH] clk: ti: dra7: fix parent for gmac_clkctrl |
| |
| commit 69e300283796dae7e8c2e6acdabcd31336c0c93e upstream. |
| |
| The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead |
| of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation. |
| Hence, fix it. |
| |
| Fixes: dffa9051d546 ('clk: ti: dra7: add new clkctrl data') |
| Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> |
| Signed-off-by: Tero Kristo <t-kristo@ti.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c |
| index 9dd6185a4b4e..66e4b2b9ec60 100644 |
| --- a/drivers/clk/ti/clk-7xx.c |
| +++ b/drivers/clk/ti/clk-7xx.c |
| @@ -405,7 +405,7 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = { |
| }; |
| |
| static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = { |
| - { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" }, |
| + { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" }, |
| { 0 }, |
| }; |
| |
| -- |
| 2.7.4 |
| |