| From 971adb8e92bfe290b9c1416aa1030c502ae8ba20 Mon Sep 17 00:00:00 2001 |
| From: Bruce Allan <bruce.w.allan@intel.com> |
| Date: Thu, 6 Feb 2020 01:20:07 -0800 |
| Subject: [PATCH] ice: update Unit Load Status bitmask to check after reset |
| |
| commit cf8fc2a0863f9ff27ebd2efcdb1f7d378b9fb8a6 upstream. |
| |
| After a reset the Unit Load Status bits in the GLNVM_ULD register to check |
| for completion should be 0x7FF before continuing. Update the mask to check |
| (minus the three reserved bits that are always set). |
| |
| Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> |
| Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> |
| Tested-by: Andrew Bowers <andrewx.bowers@intel.com> |
| Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c |
| index da7878529929..b03d414a56f9 100644 |
| --- a/drivers/net/ethernet/intel/ice/ice_common.c |
| +++ b/drivers/net/ethernet/intel/ice/ice_common.c |
| @@ -842,7 +842,7 @@ void ice_deinit_hw(struct ice_hw *hw) |
| */ |
| enum ice_status ice_check_reset(struct ice_hw *hw) |
| { |
| - u32 cnt, reg = 0, grst_delay; |
| + u32 cnt, reg = 0, grst_delay, uld_mask; |
| |
| /* Poll for Device Active state in case a recent CORER, GLOBR, |
| * or EMPR has occurred. The grst delay value is in 100ms units. |
| @@ -864,13 +864,20 @@ enum ice_status ice_check_reset(struct ice_hw *hw) |
| return ICE_ERR_RESET_FAILED; |
| } |
| |
| -#define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \ |
| - GLNVM_ULD_GLOBR_DONE_M) |
| +#define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ |
| + GLNVM_ULD_PCIER_DONE_1_M |\ |
| + GLNVM_ULD_CORER_DONE_M |\ |
| + GLNVM_ULD_GLOBR_DONE_M |\ |
| + GLNVM_ULD_POR_DONE_M |\ |
| + GLNVM_ULD_POR_DONE_1_M |\ |
| + GLNVM_ULD_PCIER_DONE_2_M) |
| + |
| + uld_mask = ICE_RESET_DONE_MASK; |
| |
| /* Device is Active; check Global Reset processes are done */ |
| for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { |
| - reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK; |
| - if (reg == ICE_RESET_DONE_MASK) { |
| + reg = rd32(hw, GLNVM_ULD) & uld_mask; |
| + if (reg == uld_mask) { |
| ice_debug(hw, ICE_DBG_INIT, |
| "Global reset processes done. %d\n", cnt); |
| break; |
| diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h |
| index ec25f26069b0..63b74424e402 100644 |
| --- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h |
| +++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h |
| @@ -264,8 +264,14 @@ |
| #define GLNVM_GENS_SR_SIZE_S 5 |
| #define GLNVM_GENS_SR_SIZE_M ICE_M(0x7, 5) |
| #define GLNVM_ULD 0x000B6008 |
| +#define GLNVM_ULD_PCIER_DONE_M BIT(0) |
| +#define GLNVM_ULD_PCIER_DONE_1_M BIT(1) |
| #define GLNVM_ULD_CORER_DONE_M BIT(3) |
| #define GLNVM_ULD_GLOBR_DONE_M BIT(4) |
| +#define GLNVM_ULD_POR_DONE_M BIT(5) |
| +#define GLNVM_ULD_POR_DONE_1_M BIT(8) |
| +#define GLNVM_ULD_PCIER_DONE_2_M BIT(9) |
| +#define GLNVM_ULD_PE_DONE_M BIT(10) |
| #define GLPCI_CNF2 0x000BE004 |
| #define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1) |
| #define PF_FUNC_RID 0x0009E880 |
| -- |
| 2.7.4 |
| |
