| From 845b4cb9f92faa3990900f01a9cd1ea03b2b06ed Mon Sep 17 00:00:00 2001 |
| From: Amelie Delaunay <amelie.delaunay@st.com> |
| Date: Fri, 28 Jun 2019 11:18:06 +0200 |
| Subject: [PATCH] mtd: rawnand: stm32_fmc2: increase DMA completion timeouts |
| |
| commit bce9437a0a48dd5e19490f56e1cdc39a9be5563c upstream. |
| |
| When the system is overloaded, DMA data transfer completion occurs after |
| 100ms. Increase the timeouts to let it the time to complete. |
| |
| Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> |
| Signed-off-by: Christophe Kerello <christophe.kerello@st.com> |
| Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c |
| index 76609b908b5e..bef9d3f9284f 100644 |
| --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c |
| +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c |
| @@ -37,6 +37,8 @@ |
| /* Max ECC buffer length */ |
| #define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG) |
| |
| +#define FMC2_TIMEOUT_MS 1000 |
| + |
| /* Timings */ |
| #define FMC2_THIZ 1 |
| #define FMC2_TIO 8000 |
| @@ -530,7 +532,8 @@ static int stm32_fmc2_ham_calculate(struct nand_chip *chip, const u8 *data, |
| int ret; |
| |
| ret = readl_relaxed_poll_timeout(fmc2->io_base + FMC2_SR, |
| - sr, sr & FMC2_SR_NWRF, 10, 1000); |
| + sr, sr & FMC2_SR_NWRF, 10, |
| + FMC2_TIMEOUT_MS); |
| if (ret) { |
| dev_err(fmc2->dev, "ham timeout\n"); |
| return ret; |
| @@ -611,7 +614,7 @@ static int stm32_fmc2_bch_calculate(struct nand_chip *chip, const u8 *data, |
| |
| /* Wait until the BCH code is ready */ |
| if (!wait_for_completion_timeout(&fmc2->complete, |
| - msecs_to_jiffies(1000))) { |
| + msecs_to_jiffies(FMC2_TIMEOUT_MS))) { |
| dev_err(fmc2->dev, "bch timeout\n"); |
| stm32_fmc2_disable_bch_irq(fmc2); |
| return -ETIMEDOUT; |
| @@ -696,7 +699,7 @@ static int stm32_fmc2_bch_correct(struct nand_chip *chip, u8 *dat, |
| |
| /* Wait until the decoding error is ready */ |
| if (!wait_for_completion_timeout(&fmc2->complete, |
| - msecs_to_jiffies(1000))) { |
| + msecs_to_jiffies(FMC2_TIMEOUT_MS))) { |
| dev_err(fmc2->dev, "bch timeout\n"); |
| stm32_fmc2_disable_bch_irq(fmc2); |
| return -ETIMEDOUT; |
| @@ -969,7 +972,7 @@ static int stm32_fmc2_xfer(struct nand_chip *chip, const u8 *buf, |
| |
| /* Wait end of sequencer transfer */ |
| if (!wait_for_completion_timeout(&fmc2->complete, |
| - msecs_to_jiffies(1000))) { |
| + msecs_to_jiffies(FMC2_TIMEOUT_MS))) { |
| dev_err(fmc2->dev, "seq timeout\n"); |
| stm32_fmc2_disable_seq_irq(fmc2); |
| dmaengine_terminate_all(dma_ch); |
| @@ -981,7 +984,7 @@ static int stm32_fmc2_xfer(struct nand_chip *chip, const u8 *buf, |
| |
| /* Wait DMA data transfer completion */ |
| if (!wait_for_completion_timeout(&fmc2->dma_data_complete, |
| - msecs_to_jiffies(100))) { |
| + msecs_to_jiffies(FMC2_TIMEOUT_MS))) { |
| dev_err(fmc2->dev, "data DMA timeout\n"); |
| dmaengine_terminate_all(dma_ch); |
| ret = -ETIMEDOUT; |
| @@ -990,7 +993,7 @@ static int stm32_fmc2_xfer(struct nand_chip *chip, const u8 *buf, |
| /* Wait DMA ECC transfer completion */ |
| if (!write_data && !raw) { |
| if (!wait_for_completion_timeout(&fmc2->dma_ecc_complete, |
| - msecs_to_jiffies(100))) { |
| + msecs_to_jiffies(FMC2_TIMEOUT_MS))) { |
| dev_err(fmc2->dev, "ECC DMA timeout\n"); |
| dmaengine_terminate_all(fmc2->dma_ecc_ch); |
| ret = -ETIMEDOUT; |
| -- |
| 2.7.4 |
| |
