| From 75cf6cfe7b15e3290a82b3cb0b5de7d15cbb4c0f Mon Sep 17 00:00:00 2001 |
| From: Wu Zhangjin <wuzhangjin@gmail.com> |
| Date: Sat, 27 Feb 2010 15:08:45 +0800 |
| Subject: [PATCH] RT: MIPS: Loongson: speedup the irq dispatch |
| |
| commit 75cf6cfe7b15e3290a82b3cb0b5de7d15cbb4c0f in tip. |
| |
| This patch annotates the irq dispatch functions as inline, this may not |
| be compiled with gcc 3.4.6, only tested with gcc 4.4.1. |
| |
| And also, this patch tries to tune the order of the interrupts to |
| speedup the interrupts from northbright and sourthbrige. |
| |
| Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> |
| |
| diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h |
| index ee8bc83..fe93e14 100644 |
| --- a/arch/mips/include/asm/mach-loongson/loongson.h |
| +++ b/arch/mips/include/asm/mach-loongson/loongson.h |
| @@ -16,7 +16,7 @@ |
| #include <linux/init.h> |
| |
| /* loongson internal northbridge initialization */ |
| -extern void bonito_irq_init(void); |
| +extern inline void bonito_irq_init(void); |
| |
| /* machine-specific reboot/halt operation */ |
| extern void mach_prepare_reboot(void); |
| @@ -48,8 +48,8 @@ extern void bonito_irqdispatch(void); |
| extern void __init bonito_irq_init(void); |
| extern void __init set_irq_trigger_mode(void); |
| extern void __init mach_init_irq(void); |
| -extern void mach_irq_dispatch(unsigned int pending); |
| -extern int mach_i8259_irq(void); |
| +extern inline void mach_irq_dispatch(unsigned int pending); |
| +extern inline int mach_i8259_irq(void); |
| |
| /* We need this in some places... */ |
| #define delay() ({ \ |
| diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c |
| index 20e7328..23345b5 100644 |
| --- a/arch/mips/loongson/common/irq.c |
| +++ b/arch/mips/loongson/common/irq.c |
| @@ -14,7 +14,7 @@ |
| /* |
| * the first level int-handler will jump here if it is a bonito irq |
| */ |
| -void bonito_irqdispatch(void) |
| +inline void bonito_irqdispatch(void) |
| { |
| u32 int_status; |
| int i; |
| diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c |
| index 3844258..3ee7bd3 100644 |
| --- a/arch/mips/loongson/fuloong-2e/irq.c |
| +++ b/arch/mips/loongson/fuloong-2e/irq.c |
| @@ -14,7 +14,7 @@ |
| |
| #include <loongson.h> |
| |
| -static void i8259_irqdispatch(void) |
| +static inline void i8259_irqdispatch(void) |
| { |
| int irq; |
| |
| @@ -25,16 +25,18 @@ static void i8259_irqdispatch(void) |
| spurious_interrupt(); |
| } |
| |
| -asmlinkage void mach_irq_dispatch(unsigned int pending) |
| +inline void mach_irq_dispatch(unsigned int pending) |
| { |
| if (pending & CAUSEF_IP7) |
| do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
| - else if (pending & CAUSEF_IP6) /* perf counter loverflow */ |
| - do_IRQ(LOONGSON2_PERFCNT_IRQ); |
| - else if (pending & CAUSEF_IP5) |
| - i8259_irqdispatch(); |
| else if (pending & CAUSEF_IP2) |
| bonito_irqdispatch(); |
| + else if (pending & CAUSEF_IP5) |
| + i8259_irqdispatch(); |
| +#ifdef CONFIG_OPROFILE |
| + else if (pending & CAUSEF_IP6) /* perf counter loverflow */ |
| + do_IRQ(LOONGSON2_PERFCNT_IRQ); |
| +#endif |
| else |
| spurious_interrupt(); |
| } |
| diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c |
| index 6387510..2120235 100644 |
| --- a/arch/mips/loongson/lemote-2f/irq.c |
| +++ b/arch/mips/loongson/lemote-2f/irq.c |
| @@ -31,7 +31,7 @@ |
| * The generic i8259_irq() make the kernel hang on booting. Since we cannot |
| * get the irq via the IRR directly, we access the ISR instead. |
| */ |
| -int mach_i8259_irq(void) |
| +inline int mach_i8259_irq(void) |
| { |
| int irq, isr; |
| |
| @@ -63,7 +63,7 @@ int mach_i8259_irq(void) |
| } |
| EXPORT_SYMBOL(mach_i8259_irq); |
| |
| -static void i8259_irqdispatch(void) |
| +static inline void i8259_irqdispatch(void) |
| { |
| int irq; |
| |
| @@ -74,7 +74,7 @@ static void i8259_irqdispatch(void) |
| spurious_interrupt(); |
| } |
| |
| -void mach_irq_dispatch(unsigned int pending) |
| +inline void mach_irq_dispatch(unsigned int pending) |
| { |
| if (pending & CAUSEF_IP7) |
| do_IRQ(LOONGSON_TIMER_IRQ); |
| @@ -83,10 +83,10 @@ void mach_irq_dispatch(unsigned int pending) |
| do_IRQ(LOONGSON2_PERFCNT_IRQ); |
| #endif |
| bonito_irqdispatch(); |
| - } else if (pending & CAUSEF_IP3) /* CPU UART */ |
| - do_IRQ(LOONGSON_UART_IRQ); |
| - else if (pending & CAUSEF_IP2) /* South Bridge */ |
| + } else if (pending & CAUSEF_IP2) /* South Bridge */ |
| i8259_irqdispatch(); |
| + else if (pending & CAUSEF_IP3) /* CPU UART */ |
| + do_IRQ(LOONGSON_UART_IRQ); |
| else |
| spurious_interrupt(); |
| } |
| -- |
| 1.7.1.1 |
| |