| #FIG 3.2 Produced by xfig version 3.2.5 |
| Landscape |
| Center |
| Inches |
| A4 |
| 100.00 |
| Single |
| -2 |
| 1200 2 |
| 6 300 3150 1650 3525 |
| 2 2 0 1 0 28 50 -1 20 0.000 0 0 -1 0 0 5 |
| 300 3150 1650 3150 1650 3525 300 3525 300 3150 |
| 4 1 0 50 -1 16 9 0.0000 4 150 990 975 3375 raise_softirq()\001 |
| -6 |
| 6 1875 2325 2100 3675 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 1875 3600 1875 2400 2100 2400 2100 3600 1875 3600 |
| 4 1 0 50 -1 16 9 1.5708 4 150 1215 2025 3000 rcu_enter_nohz()\001 |
| -6 |
| 6 2175 2400 2400 3600 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 2175 3600 2175 2400 2400 2400 2400 3600 2175 3600 |
| 4 1 0 50 -1 16 9 1.5708 4 150 1110 2325 3000 rcu_exit_nohz()\001 |
| -6 |
| 6 2475 2400 2700 3600 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 2475 3600 2475 2400 2700 2400 2700 3600 2475 3600 |
| 4 1 0 50 -1 16 9 1.5708 4 150 1050 2625 3000 rcu_irq_enter()\001 |
| -6 |
| 6 2775 2400 3000 3600 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 2775 3600 2775 2400 3000 2400 3000 3600 2775 3600 |
| 4 1 0 50 -1 16 9 1.5708 4 150 945 2925 3000 rcu_irq_exit()\001 |
| -6 |
| 6 3075 2400 3300 3600 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 3075 3600 3075 2400 3300 2400 3300 3600 3075 3600 |
| 4 1 0 50 -1 16 9 1.5708 4 150 1110 3225 3000 rcu_nmi_enter()\001 |
| -6 |
| 6 3375 2400 3600 3600 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 3375 3600 3375 2400 3600 2400 3600 3600 3375 3600 |
| 4 1 0 50 -1 16 9 1.5708 4 150 1005 3525 3000 rcu_nmi_exit()\001 |
| -6 |
| 6 2850 4050 3600 4425 |
| 2 2 0 1 0 28 50 -1 20 0.000 0 0 -1 0 0 5 |
| 2850 4050 3600 4050 3600 4425 2850 4425 2850 4050 |
| 4 1 0 50 -1 16 9 0.0000 4 150 570 3225 4275 dynticks\001 |
| -6 |
| 6 0 900 1530 1305 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 0 900 1500 900 1500 1275 0 1275 0 900 |
| 4 1 0 50 -1 16 9 0.0000 4 150 1500 750 1125 rcu_check_callbacks()\001 |
| -6 |
| 6 1800 900 2850 1275 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 1800 900 2850 900 2850 1275 1800 1275 1800 900 |
| 4 1 0 50 -1 16 9 0.0000 4 150 975 2325 1125 rcu_pending()\001 |
| -6 |
| 6 1500 0 2100 450 |
| 2 2 0 1 0 28 50 -1 20 0.000 0 0 -1 0 0 5 |
| 1500 0 2100 0 2100 450 1500 450 1500 0 |
| 4 1 0 50 -1 16 9 0.0000 4 120 240 1800 225 Idle\001 |
| 4 1 0 50 -1 16 9 0.0000 4 150 360 1800 375 Loop\001 |
| -6 |
| 6 2400 0 3615 540 |
| 2 2 0 1 0 28 50 -1 20 0.000 0 0 -1 0 0 5 |
| 2400 0 3600 0 3600 525 2400 525 2400 0 |
| 4 1 0 50 -1 16 9 0.0000 4 120 675 3000 300 Scheduler\001 |
| -6 |
| 6 0 0 1215 540 |
| 2 2 0 1 0 28 50 -1 20 0.000 0 0 -1 0 0 5 |
| 0 0 1200 0 1200 525 0 525 0 0 |
| 4 1 0 50 -1 16 9 0.0000 4 150 750 600 225 Scheduling\001 |
| 4 1 0 50 -1 16 9 0.0000 4 135 705 600 450 Clock IRQ\001 |
| -6 |
| 6 375 2400 1575 2775 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 375 2400 1575 2400 1575 2775 375 2775 375 2400 |
| 4 1 0 50 -1 16 9 0.0000 4 150 1155 975 2625 rcu_qsctr_help()\001 |
| -6 |
| 6 -75 5400 1875 5775 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 0 5400 1800 5400 1800 5775 0 5775 0 5400 |
| 4 1 0 50 -1 16 9 0.0000 4 150 1830 900 5625 __rcu_process_callbacks()\001 |
| -6 |
| 6 0 4620 1800 5025 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 0 4650 1800 4650 1800 5025 0 5025 0 4650 |
| 4 1 0 50 -1 16 9 0.0000 4 150 1650 900 4875 rcu_process_callbacks()\001 |
| -6 |
| 6 0 6825 1215 7230 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 0 6825 1200 6825 1200 7200 0 7200 0 6825 |
| 4 1 0 50 -1 16 9 0.0000 4 150 810 600 7050 __call_rcu()\001 |
| -6 |
| 6 0 7545 1215 7950 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 0 7575 1200 7575 1200 7950 0 7950 0 7575 |
| 4 1 0 50 -1 16 9 0.0000 4 150 900 600 7800 call_rcu_bh()\001 |
| -6 |
| 6 1500 7545 2715 7950 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 1500 7575 2700 7575 2700 7950 1500 7950 1500 7575 |
| 4 1 0 50 -1 16 9 0.0000 4 150 630 2100 7800 call_rcu()\001 |
| -6 |
| 6 0 6150 1215 6465 |
| 2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 |
| 1200 6450 0 6450 0 6150 1200 6150 1200 6450 |
| 4 1 0 50 -1 16 9 0.0000 4 150 990 600 6375 rcu_bh_ctrlblk\001 |
| -6 |
| 6 1425 6150 2325 6450 |
| 2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 |
| 2325 6450 1425 6450 1425 6150 2325 6150 2325 6450 |
| 4 1 0 50 -1 16 9 0.0000 4 150 720 1875 6375 rcu_ctrlblk\001 |
| -6 |
| 6 2250 6825 3600 7200 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 2250 6825 3600 6825 3600 7200 2250 7200 2250 6825 |
| 4 1 0 50 -1 16 9 0.0000 4 150 1245 2925 7050 synchronize_rcu()\001 |
| -6 |
| 6 300 3900 1650 4275 |
| 2 2 0 1 0 28 50 -1 20 0.000 0 0 -1 0 0 5 |
| 300 3900 1650 3900 1650 4275 300 4275 300 3900 |
| 4 1 0 50 -1 16 9 0.0000 4 150 1035 975 4125 __do_softirq()\001 |
| -6 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 0 1650 1350 1650 1350 2025 0 2025 0 1650 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 1575 1875 1200 2400 |
| 2 1 3 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 |
| 2 1 1.00 60.00 120.00 |
| 600 3525 600 3900 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 2025 3900 2025 3600 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 2325 3900 2325 3600 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 2625 3900 2625 3600 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 2925 3900 2925 3600 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 3225 3900 3225 3600 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 3525 3900 3525 3600 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 |
| 2025 3900 3525 3900 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 |
| 3225 4050 3225 3900 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 1950 2400 1950 2025 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 |
| 0 0 1.00 60.00 120.00 |
| 2850 2400 2850 2100 2025 2100 2025 2400 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 |
| 0 0 1.00 60.00 120.00 |
| 2550 2400 2550 2175 2325 2175 2325 2400 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 2400 4800 3600 4800 3600 5175 2400 5175 2400 4800 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 3225 4425 3225 4800 |
| 2 2 0 1 0 11 50 -1 20 0.000 0 0 -1 0 0 5 |
| 1575 1650 2925 1650 2925 2025 1575 2025 1575 1650 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 1650 450 1050 900 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 1950 450 2325 900 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 750 2025 750 2400 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 3150 525 2850 1650 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 761 1275 536 1650 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 1359 1275 1659 1650 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 600 525 600 900 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 903 510 1800 975 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 1800 2025 1575 3150 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 |
| 0 0 1.00 60.00 120.00 |
| 225 2025 225 2850 450 3150 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 600 5025 600 5400 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 1200 5025 1200 5400 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 600 6150 600 5775 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 1875 6150 1500 5775 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 600 6825 600 6450 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 975 6825 1875 6450 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 600 7575 600 7200 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 1800 7575 975 7200 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 |
| 0 0 1.00 60.00 120.00 |
| 900 4275 900 4650 |
| 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 |
| 0 0 1.00 60.00 120.00 |
| 300 4050 75 4050 75 2025 |
| 4 1 0 50 -1 16 9 0.0000 4 150 1155 3000 5025 rcu_needs_cpu()\001 |
| 4 1 0 50 -1 16 9 0.0000 4 150 1335 675 1875 rcu_bh_qsctr_inc()\001 |
| 4 1 0 50 -1 16 9 0.0000 4 150 1065 2250 1875 rcu_qsctr_inc()\001 |