appendix/rcuimpl/RCUpreemptValidation.fig

#FIG 3.2  Produced by xfig version 3.2.5
Landscape
Center
Inches
A4      
100.00
Single
-2
1200 2
6 450 3225 2325 3450
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 3300 750 3300
4 0 0 50 -1 16 9 0.0000 4 150 1455 825 3375 Old counters zero [0]\001
-6
6 525 1950 1575 2100
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 2025 750 2025
4 0 0 50 -1 16 9 0.0000 4 120 750 825 2100 CPU 2 ack\001
-6
6 525 2175 1575 2325
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 2250 750 2250
4 0 0 50 -1 16 9 0.0000 4 120 750 825 2325 CPU 3 ack\001
-6
6 525 2475 1575 2625
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 2550 750 2550
4 0 0 50 -1 16 9 0.0000 4 120 750 825 2625 CPU 1 ack\001
-6
6 525 2625 1575 2775
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 2700 750 2700
4 0 0 50 -1 16 9 0.0000 4 120 750 825 2775 CPU 0 ack\001
-6
6 525 3525 1575 3675
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 3600 750 3600
4 0 0 50 -1 16 9 0.0000 4 120 735 825 3675 CPU 3 mb\001
-6
6 525 3675 1575 3825
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 3750 750 3750
4 0 0 50 -1 16 9 0.0000 4 120 735 825 3825 CPU 0 mb\001
-6
6 525 3975 1575 4125
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 4050 750 4050
4 0 0 50 -1 16 9 0.0000 4 120 735 825 4125 CPU 2 mb\001
-6
6 525 5550 1575 5700
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 5625 750 5625
4 0 0 50 -1 16 9 0.0000 4 120 750 825 5700 CPU 0 ack\001
-6
6 525 7050 1575 7200
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 7125 750 7125
4 0 0 50 -1 16 9 0.0000 4 120 735 825 7200 CPU 1 mb\001
-6
6 525 6375 1575 6525
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 6450 750 6450
4 0 0 50 -1 16 9 0.0000 4 120 735 825 6525 CPU 3 mb\001
-6
6 525 6825 1575 6975
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 6900 750 6900
4 0 0 50 -1 16 9 0.0000 4 120 735 825 6975 CPU 2 mb\001
-6
6 525 6675 1575 6825
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 6750 750 6750
4 0 0 50 -1 16 9 0.0000 4 120 735 825 6825 CPU 0 mb\001
-6
6 525 5325 1575 5475
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 5400 750 5400
4 0 0 50 -1 16 9 0.0000 4 120 750 825 5475 CPU 1 ack\001
-6
6 525 5175 1575 5325
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 5250 750 5250
4 0 0 50 -1 16 9 0.0000 4 120 750 825 5325 CPU 2 ack\001
-6
6 525 5025 1575 5175
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 5100 750 5100
4 0 0 50 -1 16 9 0.0000 4 120 750 825 5175 CPU 3 ack\001
-6
6 525 8025 1575 8175
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 8100 750 8100
4 0 0 50 -1 16 9 0.0000 4 120 750 825 8175 CPU 0 ack\001
-6
6 525 8175 1575 8325
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 8250 750 8250
4 0 0 50 -1 16 9 0.0000 4 120 750 825 8325 CPU 3 ack\001
-6
6 525 8400 1575 8550
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 8475 750 8475
4 0 0 50 -1 16 9 0.0000 4 120 750 825 8550 CPU 1 ack\001
-6
6 525 8625 1575 8775
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 8700 750 8700
4 0 0 50 -1 16 9 0.0000 4 120 750 825 8775 CPU 2 ack\001
-6
6 450 6150 2325 6375
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 6225 750 6225
4 0 0 50 -1 16 9 0.0000 4 150 1455 825 6300 Old counters zero [1]\001
-6
6 525 525 1575 675
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 600 750 600
4 0 0 50 -1 16 9 0.0000 4 120 735 825 675 CPU 1 mb\001
-6
6 525 1200 1575 1350
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 1275 750 1275
4 0 0 50 -1 16 9 0.0000 4 120 735 825 1350 CPU 0 mb\001
-6
6 525 1050 1575 1200
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 1125 750 1125
4 0 0 50 -1 16 9 0.0000 4 120 735 825 1200 CPU 3 mb\001
-6
6 525 4125 1575 4275
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 4200 750 4200
4 0 0 50 -1 16 9 0.0000 4 120 735 825 4275 CPU 1 mb\001
-6
6 525 825 1575 975
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 525 900 750 900
4 0 0 50 -1 16 9 0.0000 4 120 735 825 975 CPU 2 mb\001
-6
1 2 0 1 11 11 60 -1 20 0.000 1 0.0000 600 2100 150 600 450 2100 750 2100
1 2 0 1 11 11 60 -1 20 0.000 1 0.0000 600 5025 150 600 450 5025 750 5025
1 2 0 1 11 11 60 -1 20 0.000 1 0.0000 600 8100 150 600 450 8100 750 8100
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 450 1725 750 1725
2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	 600 1275 0 1275
2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	 600 1725 0 1725
2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	 600 2700 0 2700
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
	0 0 1.00 60.00 120.00
	0 0 1.00 60.00 120.00
	 225 1275 225 1725
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
	0 0 1.00 60.00 120.00
	0 0 1.00 60.00 120.00
	 225 1725 225 2700
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
	0 0 1.00 60.00 120.00
	0 0 1.00 60.00 120.00
	 225 2700 225 3300
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
	0 0 1.00 60.00 120.00
	0 0 1.00 60.00 120.00
	 225 3300 225 4200
2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	 600 3300 0 3300
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 450 4650 750 4650
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
	 450 7800 750 7800
2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	 600 4200 0 4200
2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	 600 4650 0 4650
2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	 600 5625 0 5625
2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	 600 7125 0 7125
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
	0 0 1.00 60.00 120.00
	0 0 1.00 60.00 120.00
	 225 4200 225 4650
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
	0 0 1.00 60.00 120.00
	0 0 1.00 60.00 120.00
	 225 4650 225 5625
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
	0 0 1.00 60.00 120.00
	0 0 1.00 60.00 120.00
	 225 5625 225 6225
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
	0 0 1.00 60.00 120.00
	0 0 1.00 60.00 120.00
	 225 6225 225 7125
2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	 600 7800 0 7800
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
	0 0 1.00 60.00 120.00
	0 0 1.00 60.00 120.00
	 225 7125 225 7800
2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	 600 6225 0 6225
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
	0 0 1.00 60.00 120.00
	0 0 1.00 60.00 120.00
	 225 7800 225 8700
2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	 600 8700 0 8700
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
	1 1 1.00 60.00 120.00
	 600 375 600 9150
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
	0 0 1.00 60.00 120.00
	 225 375 225 1275
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
	1 1 1.00 60.00 120.00
	 3000 375 3000 9150
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
	1 1 1.00 60.00 120.00
	 5400 375 5400 9150
2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
	 1650 600 7200 600
2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
	 1650 5100 7200 5100
2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
	 1650 2700 7200 2700
2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
	 1650 5625 7200 5625
2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
	 2400 6225 7200 6225
2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
	 1650 7125 7200 7125
2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
	 2250 1725 7200 1725
2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
	 1650 2550 7200 2550
2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2
	 1650 8100 7200 8100
2 3 0 1 7 2 60 -1 20 0.000 0 0 -1 0 0 9
	 5100 2850 5700 2850 5700 1350 6150 1350 5400 900 4650 1350
	 5100 1350 5100 3000 5100 2850
2 3 0 1 7 2 60 -1 20 0.000 0 0 -1 0 0 9
	 5100 5850 5700 5850 5700 6375 6150 6375 5400 6825 4650 6375
	 5100 6375 5100 4725 5100 5850
4 0 0 50 -1 16 9 1.5708 4 120 225 150 1575 idle\001
4 1 0 50 -1 16 9 1.5708 4 120 510 150 2175 waitack\001
4 1 0 50 -1 16 9 1.5708 4 120 585 150 3000 waitzero\001
4 1 0 50 -1 16 9 1.5708 4 120 495 150 3750 waitmb\001
4 0 0 50 -1 16 9 0.0000 4 150 1260 825 4725 completed++ [==2]\001
4 0 0 50 -1 16 9 0.0000 4 150 1260 825 7875 completed++ [==3]\001
4 0 0 50 -1 16 9 1.5708 4 120 225 150 4500 idle\001
4 1 0 50 -1 16 9 1.5708 4 120 510 150 5100 waitack\001
4 0 0 50 -1 16 9 1.5708 4 120 225 150 7575 idle\001
4 1 0 50 -1 16 9 1.5708 4 120 585 150 5925 waitzero\001
4 1 0 50 -1 16 9 1.5708 4 120 510 150 8100 waitack\001
4 1 0 50 -1 16 9 1.5708 4 120 495 150 6675 waitmb\001
4 1 0 50 -1 16 9 1.5708 4 120 495 150 900 waitmb\001
4 1 0 50 -1 16 9 0.0000 4 120 990 600 300 State Machine\001
4 1 0 50 -1 16 9 0.0000 4 120 915 600 150 Grace-Period\001
4 1 0 50 -1 16 9 0.0000 4 120 825 3000 300 Reclamation\001
4 1 0 50 -1 16 9 0.0000 4 120 885 3000 150 Removal and\001
4 1 0 50 -1 16 9 0.0000 4 120 1095 5400 150 RCU Read-Side\001
4 1 0 50 -1 16 9 0.0000 4 120 1050 5400 300 Critical Section\001
4 1 0 50 -1 16 9 0.0000 4 150 2130 5400 675 Earliest Possible Reordering of\001
4 1 0 50 -1 14 9 0.0000 4 135 1530 5400 825 rcu_dereference()\001
4 1 0 50 -1 16 9 0.0000 4 120 1980 5400 6150 Latest Possible Execution of\001
4 1 0 50 -1 14 9 0.0000 4 135 1530 5400 6300 rcu_read_unlock()\001
4 1 0 50 -1 16 9 0.0000 4 150 2055 5400 6975 Latest Possible Reordering of\001
4 1 0 50 -1 16 9 0.0000 4 120 1965 5400 7125 RCU-Protected Pointer Use\001
4 1 0 50 -1 16 9 0.0000 4 120 1905 3000 8325 Earliest Possible Invocation\001
4 1 0 50 -1 14 9 0.0000 4 120 1350 3000 8175 wait[1] to done\001
4 1 0 50 -1 14 9 0.0000 4 120 1350 3000 2775 next to wait[0]\001
4 1 0 50 -1 14 9 0.0000 4 135 900 3000 2625 call_rcu()\001
4 1 0 50 -1 14 9 0.0000 4 135 1260 3000 2475 list_del_rcu()\001
4 1 0 50 -1 16 9 0.0000 4 150 2055 5400 2400 Latest Possible Reordering of\001
4 1 0 50 -1 14 9 0.0000 4 135 1350 5400 2550 rcu_read_lock()\001
4 1 0 50 -1 14 9 0.0000 4 120 1620 3000 5700 wait[0] to wait[1]\001
4 0 0 50 -1 16 9 0.0000 4 150 1260 825 1800 completed++ [==1]\001