bib/hw.bib

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and Zurek",
}

@article{ErwinSchroedinger1935Cat,
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@ARTICLE{1957PhRv..105.1413W,
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}

@phdthesis{JohnAmosBolesPhD,
 author="John Amos Boles",
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@article{Gharachorloo:1990:MCE:325096.325102,
 author = {Gharachorloo, Kourosh and Lenoski, Daniel and Laudon, James and Gibbons, Phillip and Gupta, Anoop and Hennessy, John},
 title = {Memory Consistency and Event Ordering in Scalable Shared-memory Multiprocessors},
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 year = {1990},
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}

@article{Miller94,
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@Article{Alpern94,
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@Book{IEEE1596SCI91,
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@conference{Torrellas92,
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@Book{Hennessy95a,
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@Book{Hennessy2011,
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@Book{DavidECuller1999,
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@unpublished{CSIRACMuseumVictoria,
 Author="{Museum Victoria Australia}",
 Title="{CSIRAC}: {Australia's} First Computer",
 year="2004",
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\url{http://museumvictoria.com.au/csirac/}",
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@unpublished{CSIRACUniversityMelbourne,
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of Melbourne}",
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 year="2006",
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@unpublished{z80Wikipedia,
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[Viewed: December 7, 2008]",
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@manual{AMDOpteron02,
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}

@manual{AMDOpteron:2:2007,
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System Programming",
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 year="2007",
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}

@unpublished{AMD2017OpenCL,
 Author="AMD",
 Title="{OpenCL\textsuperscript\texttrademark} Zone---Accelerate Your Applications",
 year="2017",
 month="January",
 note="\nolinkurl{http://developer.amd.com/tools-and-sdks/opencl-zone/} (Obsolete, see bibentry AMD2020ROCm)",
}

@unpublished{AMD2020ROCm,
 Author="AMD",
 Title="Professional Compute Products - {GPUOpen}",
 year="2020",
 month="March",
 note="\url{https://gpuopen.com/professional-compute/}",
}


@manual{ARMv8Litmus2009,
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}

@manual{ARMv7A:2010,
 title="ARM Architecture Reference Manual: ARMv7-A and ARMv7-R Edition",
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 year="2010",
 number="ARMDDI0406B_errata_2009_Q4 ID022510",
}

@unpublished{ARMLeif2011MemoryOrdering1,
 Author="ARM Leif",
 Title="Memory access ordering - an introduction",
 year="2011",
 month="March",
 url={http://blogs.arm.com/software-enablement/431-memory-access-ordering-an-introduction/},
}

@unpublished{ARMLeif2011MemoryOrdering2,
 Author="ARM Leif",
 Title="Memory access ordering part 2 - barriers and the {Linux} kernel",
 year="2011",
 month="April",
 url={http://blogs.arm.com/software-enablement/448-memory-access-ordering-part-2-barriers-and-the-linux-kernel/},
}

@unpublished{ARMLeif2011MemoryOrdering3,
 Author="ARM Leif",
 Title="Memory access ordering part 3 - memory access ordering in the ARM Architecture",
 year="2011",
 month="October",
 url={http://blogs.arm.com/software-enablement/594-memory-access-ordering-part-3-memory-access-ordering-in-the-arm-architecture/},
}

@manual{ARMv8A:2017,
 title="ARM Architecture Reference Manual ({ARMv8}, for {ARMv8-A} architecture profile)",
 organization="ARM Limited",
 year="2017",
 number="ARM DDI 0487B.a (ID033117)",
}

@unpublished{CoreTileExpress2012,
 Author="{ARM Ltd.}",
 Title="{CoreTile} {Express} {A15x2} {A7x3} Technical Reference Manual",
 year="2012",
 month="July",
 note="\url{http://www.arm.com/files/pdf/DDI0503B_v2p_ca15_a7_reference_manual.pdf}",
}

@unpublished{LucMaranget2017aarch64,
 Author="Luc Maraget",
 Title="AArch64 Model vs. Hardware",
 year="2017",
 month="May",
 note="\url{http://pauillac.inria.fr/~maranget/cats7/model-aarch64/specific.html}",
}


@manual{CDC3300arch70,
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 year="1970",
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}


@book{PDP12-1969,
 title="{PDP-12} User Handbook (Preliminary)",
 author="{Digital Equipment Corporation}",
 publisher="Digital Press",
 year="1969",
}

@unpublished{HewlettPackard05a,
 Author="{Hewlett Packard}",
 Title="{HP} {OpenVMS} Systems Documentation",
 year="2005",
 note="Available:
\url{http://h71000.www7.hp.com/doc/72final/4515/4515pro_contents.html}
[Viewed: February 27, 2005]",
}

@book{ALPHA95,
 title="Alpha {AXP} Architecture",
 author="Richard L. Sites and Richard T. Witek",
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 edition="second",
}

@book{ALPHA2002,
 title="Alpha Architecture Reference Manual",
 author={Compaq Computer Corporation},
 publisher="Digital Press",
 year="2002",
 edition="fourth",
}

@unpublished{Compaq01,
 Author="{Compaq Computer Corporation}",
 Title="Shared Memory, Threads, Interprocess Communication",
 month="August",
 year="2001",
 note="Zipped archive: \path{wiz_2637.txt} in
\url{https://www.digiater.nl/openvms/freeware/v70/ask_the_wizard/wizard.zip}",
}

@unpublished{MichaelCree2010AlphaLinux,
 Author="Paul E. McKenney",
 Title="Re: memory barrier question",
 month="September",
 year="2010",
 day="22",
 note="Available:
\url{https://lkml.org/lkml/2010/9/22/283}
[Viewed: June 23, 2004]",
}

@unpublished{WilliamPugh2000Gharachorloo,
 Author="William Pugh",
 Title="Reordering on an {Alpha} processor",
 year="2000",
 note="Available:
\url{https://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html}
[Viewed: June 23, 2004]",
}


@book{GerryKane96a,
 title="{PA-RISC} 2.0 Architecture",
 author="Gerry Kane",
 publisher="Hewlett-Packard Professional Books",
 year="1996",
}


@techreport{JFennel1973SMT,
 author="J. Fennel",
 title="Instruction selection in a two-program counter instruction unit",
 institution="Assigned to International Business Machines Corp",
 address="Washington, DC",
 year="1973",
 number="US Patent 3,728,692",
 month="April",
 pages="10",
}

@article{Stone:1995:SP:623262.623912,
 author = {Stone, Janice M. and Fitzgerald, Robert P.},
 title = {Storage in the {PowerPC}},
 journal = {IEEE Micro},
 issue_date = {April 1995},
 volume = {15},
 number = {2},
 month = apr,
 year = {1995},
 issn = {0272-1732},
 pages = {50--58},
 numpages = {9},
 url = {http://dx.doi.org/10.1109/40.372352},
 doi = {10.1109/40.372352},
 acmid = {623912},
 publisher = {IEEE Computer Society Press},
 address = {Los Alamitos, CA, USA},
 keywords = {PowerPC, storage, microprocessor latency},
}

@unpublished{MichaelLyons05a,
 Author="Michael Lyons and Bill Hay and Brad Frey",
 Title="{PowerPC} Storage Model and {AIX} Programming",
 month="November",
 year="2005",
 day="16",
 note="\url{http://www.ibm.com/developerworks/systems/articles/powerpc.html}",
}

@unpublished{IBMzSeries04a,
 Author="{International Business Machines Corporation}",
 Title="{z/Architecture} Principles of Operation",
 month="May",
 year="2004",
 note="Available:
\url{http://publibz.boulder.ibm.com/epubs/pdf/dz9zr003.pdf}
[Viewed: February 16, 2005]",
}

@manual{PowerPC94,
 title="PowerPC Microprocessor Family: The Programming Environments",
 organization="{IBM Microelectronics and Motorola}",
 year="1994",
 number="MPRPPCFPE-01 and MPCFPE/AD",
}

@unpublished{PaulEMcKenneyN2745r2009,
 author="Paul E. McKenney and Raul Silvera",
 title="Example POWER Implementation for C/C++ Memory Model",
 month="February",
 year="2009",
 note="Available:
\url{http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2009.02.27a.html}
[Viewed: April 5, 2009]",
}

@manual{PowerISA2.07-2013,
 title="Power {ISA} Version 2.07",
 organization="{International Business Machines Corporation}",
 year="2013",
 number="Power ISA 2.07",
}


@manual{Intel80486,
 title="i486 Microprocessor Programmer's Reference Manual",
 organization="Intel Corporation",
 year="1990",
 number="240486-001",
}

@manual{IntelPentiumProV2-96a,
 title="Pentium Pro Family Developer's Manual Volume 2:
Programmer's Reference Manual",
 organization="Intel Corporation",
 year="1996",
 month="January",
 number="242691",
}

@manual{IntelPentiumProV3-96a,
 title="Pentium Pro Family Developer's Manual Volume 3:
Operating System Writer's Guide",
 organization="Intel Corporation",
 year="1996",
 month="January",
 number="242692",
}

@manual{IntelXeonV1-96a,
 title="IA-32 Intel Architecture Software Developer's Manual Volume 1:
Basic Architecture",
 organization="{Intel Corporation}",
 year="2004",
 number="253665",
 note="Available:
\url{ftp://download.intel.com/design/Pentium4/manuals/25366514.pdf}
[Viewed: February 16, 2005]",
}

@manual{IntelXeonV2a-96a,
 title="IA-32 Intel Architecture Software Developer's Manual Volume 2A:
Instruction Set Reference, A-M",
 organization="{Intel Corporation}",
 year="2004",
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 note="Available:
\url{ftp://download.intel.com/design/Pentium4/manuals/25366614.pdf}
[Viewed: February 16, 2005]",
}

@manual{IntelXeonV2b-96a,
 title="IA-32 Intel Architecture Software Developer's Manual Volume 2B:
Instruction Set Reference, N-Z",
 organization="{Intel Corporation}",
 year="2004",
 number="253667",
 note="Available:
\url{ftp://download.intel.com/design/Pentium4/manuals/25366714.pdf}
[Viewed: February 16, 2005]",
}

@manual{IntelXeonV3-96a,
 title="IA-32 Intel Architecture Software Developer's Manual Volume 3:
System Programming Guide",
 organization="{Intel Corporation}",
 year="2004",
 number="253668",
 note="Available:
\url{ftp://download.intel.com/design/Pentium4/manuals/25366814.pdf}
[Viewed: February 16, 2005]",
}

@manual{IntelItanium02v3,
 title="Intel Itanium Architecture Software Developer's Manual
Volume 3: Instruction Set Reference",
 organization="{Intel Corporation}",
 year="2002",
 number="245319",
}

@manual{IntelItanium02v2,
 title="Intel Itanium Architecture Software Developer's Manual
Volume 3: System Architecture",
 organization="{Intel Corporation}",
 year="2002",
 number="245318",
}

@manual{IntelItaniumMemoryOrdering2002,
 title="A Formal Specification of Intel Itanium Processor Family Memory
Ordering",
 organization="{Intel Corporation}",
 year="2002",
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 note="Available:
\url{http://developer.intel.com/design/itanium/downloads/251429.htm}
\url{ftp://download.intel.com/design/Itanium/Downloads/25142901.pdf}
[Viewed: January 10, 2007]",
}

@manual{MIPSvII-A-2015,
 title="MIPS\textregistered Architecture For Programmers
Volume II-A: The MIPS64\textregistered Instruction
Set Reference Manual",
 organization="{Imagination Technologies, LTD.}",
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 number="MD00087 Rev. 6.04",
 note={\url{https://imgtec.com/?do-download=4302}},
}

@manual{MIPSvII-A-2017,
 title="{MIPS}\textregistered Architecture For Programmers
Volume II-A: The {MIPS64}\textregistered Instruction
Set Reference Manual",
 organization="{Imagination Technologies, LTD.}",
 year="2017",
 number="MD00087 Rev. 6.05",
 note={\url{https://imgtec.com/?do-download=4302}},
}

@unpublished{LinusTorvalds2006LockingPatchQuality,
 author="Linux Torvalds",
 title="Open Forum on OS Architecture for Multicore and Manycore Platforms",
 day="9",
 month="November",
 year="2006",
 note="Panel Discussion, hosted by Intel Research Council Scalable Systems Committee",
}

@manual{Intelx86MemoryOrdering2007,
 title="Intel 64 Architecture Memory Ordering White Paper",
 organization="{Intel Corporation}",
 year="2007",
 number="318147-001",
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\url{http://developer.intel.com/products/processor/manuals/318147.pdf}
[Viewed: September 7, 2007]",
}

@manual{Intel64IA32v3A2009,
 title="Intel 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A: System Programming Guide, Part 1",
 organization="{Intel Corporation}",
 year="2009",
 number="253668-030US",
 note="Available:
\url{http://download.intel.com/design/processor/manuals/253668.pdf}
[Viewed: November 8, 2009]",
}

@manual{Intel64IA32v3A2011,
 title="Intel 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A: System Programming Guide, Part 1",
 organization="{Intel Corporation}",
 year="2011",
 number="253668-037US",
 note="Available:
\url{http://www.intel.com/Assets/PDF/manual/253668.pdf}
[Viewed: February 12, 2011]",
}

@unpublished{RaviRajwar2012TSX,
 author="Ravi Rajwar and Martin Dixon",
 title="Intel Transactional Synchronization Extensions",
 month="September",
 year="2012",
 note="Intel Developer Forum (IDF) 2012 ARCS004",
}


@unpublished{CyrilZeller2011GPGPUbasics,
 Author="Cyril Zeller",
 Title="{CUDA} {C/C++} Basics: {Supercomputing} 2011 Tutorial",
 year="2011",
 month="November",
 note="\url{https://www.nvidia.com/docs/IO/116711/sc11-cuda-c-basics.pdf}",
}

@unpublished{NVidia2017GPGPU,
 Author="NVidia",
 Title="Accelerated Computing --- Training",
 year="2017",
 month="January",
 note="\url{https://developer.nvidia.com/accelerated-computing-training}",
}

@unpublished{NVidia2017GPGPU-university,
 Author="NVidia",
 Title="Existing University Courses",
 year="2017",
 month="January",
 note="\url{https://developer.nvidia.com/educators/existing-courses}",
}


@article{Thakkar1988a,
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 pages="57-69",
}

@manual{SymmetryArch90,
 title="Symmetry Multiprocessing Architecture Overview",
 organization="Sequent Computer Systems, Inc.",
 year="1990",
 number="1003-50113-00",
}


@manual{SPARC94,
 title="The {SPARC} Architecture Manual",
 organization="SPARC International",
 year="1994",
 number="ISBN 0-13-099227-5",
}


@article{Veen86,
 author="Arthur H. Veen",
 title="Dataflow Machine Architecture",
 Year="1986",
 journal="ACM Computing Surveys:",
}


@article{Lilja93,
 author="David J. Lilja",
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Issues and Comparisons",
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 Month="September",
 pages="303-338",
 Journal="ACM Computing Surveys",
}

@techreport{Gharachorloo95,
 author="Kourosh Gharachorloo",
 title="Memory Consistency Models for Shared-Memory Multiprocessors",
 institution="Computer Systems Laboratory,
Departments of Electrical Engineering and Computer Science,
Stanford University",
 address="Stanford, CA",
 year="1995",
 month="December",
 number="CSL-TR-95-685",
 note="Available:
\url{http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-9.pdf}
[Viewed: October 11, 2004]",
}

@unpublished{GilNeiger2000a,
 author="Gil Neiger",
 title="A Taxonomy of Multiprocessor Memory-Ordering Models",
 month="October",
 year="2000",
 note="Available:
\url{http://www.cs.utah.edu/mpv/papers/neiger/fmcad2001.pdf}
[Viewed: September 18, 2007]",
}

@article{RobertCSteinke2004,
 author = {Robert C. Steinke and Gary J. Nutt},
 title = {A unified theory of shared memory consistency},
 journal = {J. ACM},
 volume = {51},
 number = {5},
 year = {2004},
 issn = {0004-5411},
 pages = {800--849},
 doi = {10.1145/1017460.1017464},
 note="Available:
\url{http://arxiv.org/PS_cache/cs/pdf/0208/0208027.pdf}
[Viewed: October 19, 2006]",
 publisher = {ACM Press},
 address = {New York, NY, USA},
}


@article{HISmith90,
 author="Henry I. Smith and Dmitri A. Antoniadis",
 title="Seeking a Radically New Electronics",
 Year="1990",
 Month="April",
 institution="Massachusetts Institute of Technology",
 journal="Technology Review",
 volume="93",
 number="3",
 pages="26-40",
}

@phdthesis{Hagersten92,
 author="Erik Hagersten",
 title="Toward Scalable Cache Only Memory Architectures",
 school="Royal Institute of Technology",
 year="1992",
 address="Stockholm, Sweden",
 month=October,
}

@article{Hennessy91,
 author="John L. Hennessy and Norman P. Jouppi",
 Title="Computer Technology and Architecture: An Evolving Interaction",
 Year="1991",
 Month="September",
 pages="18-28",
 Journal="IEEE Computer",
}

@article{Stone91,
 author="Harold S. Stone and John Cocke",
 Title="Computer Architecture in the 1990s",
 Year="1991",
 Month="September",
 pages="30-38",
 Journal="IEEE Computer",
}

@article{Prince94,
 author="Betty Prince",
 Title="Memory in the Fast Lane",
 Year="1994",
 Month="February",
 pages="38--41",
 Journal="IEEE Spectrum",
}

@conference{Burger96,
 author="Doug Burger and James R. Goodman and Alain Kagi",
 title="Memory bandwidth limitations of future microprocessors",
 year="1996",
 month="May",
 booktitle="The 23\textsuperscript{rd} Annual International Symposium
on Computer Architecture",
 address = "New York, NY",
 pages="78-89",
}

@unpublished{JimGray2002SmokingHairyGolfBalls,
 author="Jim Gray",
 title="Super-Servers: Commodity Computer Clusters Pose a Software Challenge",
 day="27",
 month="April",
 year="2002",
 note="Available:
\url{http://research.microsoft.com/en-us/um/people/gray/papers/superservers(4t_computers).doc}
[Viewed: June 23, 2004]",
}

@inproceedings{GordonMoore03a,
 author="Gordon Moore",
 title="No Exponential is Forever--But we can Delay Forever",
 booktitle="IBM Academy of Technology 2003 Annual Meeting",
 year="2003",
 month="October",
 address="San Francisco, CA",
}

@unpublished{Gelsinger04a,
 author="Patrick Gelsinger",
 title="Intel Development Forum Keynote",
 month="February",
 year="2004",
 note="Available:
\url{http://www.intel.com/pressroom/archive/speeches/gelsinger20040219.htm}
[Viewed: June 23, 2004]",
}

@unpublished{BryanGardiner2007,
 author="Bryan Gardiner",
 title="{IDF}: {Gordon} {Moore} Predicts End of {Moore's} Law (Again)",
 month="September",
 year="2007",
 note="Available:
\url{http://blog.wired.com/business/2007/09/idf-gordon-mo-1.html}
[Viewed: November 28, 2008]",
}

@article{JohnKnickerbocker2008:3DI,
 author="John U. Knickerbocker",
 title="{3D} Chip Technology",
 journal="IBM Journal of Research and Development",
 Publisher="IBM",
 Month="November",
 Year="2008",
 Volume="52",
 Number="6",
 note="URL:
\url{http://www.research.ibm.com/journal/rd52-6.html}
[Link to each article is broken as of November 2016; Available via
\url{http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=5388557}]",
 lastchecked="November 13, 2016",
}

@unpublished{MichaelJKelly2017DeviceLevel,
 Author="Michael J. Kelly",
 Title="How Might the Manufacturability of the Hardware at Device Level Impact on Exascale Computing?",
 year="2017",
 note="URL:
\url{https://openparallel.com/multicore-world-2017/program-2017/abstracts2017/}",
 lastchecked="November 14, 2016",
}


@article{Lenoski93,
 author="Daniel Lenoski and James Laudon and Truman Joe and David Nakahira and
Luis Stevens and Anoop Gupta and John Hennessy",
 title="The {DASH} Prototype: Logic Overhead and Performance",
 year="1993",
 month="January",
 journal="IEEE Transactions on Parallel and Distributed Systems",
 volume="4",
 number="1",
 pages="41-61",
}


@article{TrevorMudge2000Power,
 author="Trevor Mudge",
 title="{POWER}: A First-Class Architectural Design Constraint",
 Year="2001",
 journal="IEEE Computer",
 volume="34",
 number="4",
 month="April",
 pages="52-58",
 doi="10.1109/2.917539",
}


@unpublished{PeterSewell2010weakmemory,
 author="Peter Sewell",
 title="The Semantics of Multiprocessor Programs",
 note="Available:
\url{http://www.cl.cam.ac.uk/~pes20/weakmemory/}
[Viewed: June 7, 2010]",
}

@inproceedings{SusmitSarkar2011CppPower,
 author="Susmit Sarkar and Peter Sewell and Jade Alglave and Luc Maranget and Derek Williams",
 title="Understanding {POWER} Multiprocessors",
 booktitle="Programming Language Design and Implementation (PLDI) 2011",
 year="2011",
 month="June",
 address="San Jose, CA, USA",
 url="http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/pldi105-sarkar.pdf",
}

@inproceedings{SusmitSarkar2012CppPower,
 author="Susmit Sarkar and Kayvan Memarian and Scott Owens and Mark Batty and Peter Sewell and Luc Maranget and Jade Alglave and Derek Williams",
 title="Synchronizing {C/C++} and {POWER}",
 booktitle="Programming Language Design and Implementation (PLDI) 2012",
 year="2012",
 month="June",
 address="Beijing, China",
 url="http://www.cl.cam.ac.uk/~pes20/cppppc-supplemental/pldi010-sarkar.pdf",
}

@inproceedings{BChoi2011MemoryHierarchy,
 author="Byn Choi and Rakesh Komuravelli and Hyojin Sung and Robert Smolinski and Nima Honarmand and Sarita V. Adve and Vikram S. Adve and Nicholas P. Carter and Ching-Tsun Chou",
 title="{DeNovo}: Rethinking the memory hierarchy for disciplined parallelism",
 booktitle="Proceedings of the 20\textsuperscript{th} International Conference on Parallel Architectures and Compilation Techniques (Galveston Island, TX USA)",
 year="2011",
 month="October",
 day="10-14",
 publisher="IEEE Computer Society",
 address="Washington, DC USA",
 pages="155-166",
}

@inproceedings{JHoward2010,
 author="Jason Howard and Saurabh Dighe and Yatin Hoskote and Sriram Vanagal and David Finan and Gregory Ruhl and David Jenkins and Howard Wilson and Nitin Borkar and Gerhard Schrom and Fabrice Pailet and Shailendra Jain and Tiju Jacob and Satish Yada and Sraven Marella and Praveen Salihundam and Vasantha Erraguntly and Michael Konow and Michael Riepen and Guido Droege and Joerg Lindemann and Matthias Gries and Thomas Apel and Kersten Henriss and Tor Lund-Larsen and Sebastian Steibl and Shekhar Borkar and Vivek De and Rob Van Der Wijngaart and Timothy Mattson",
 title="A 48-Core {IA-32} message-passing processor with {DVFS} in 45nm {CMOS}",
 booktitle="Proceedings of the 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers",
 year="2010",
 month="February",
 day="7-11",
 publisher="IEEE",
 address="Washington, DC USA",
 pages="108-109",
}

@article{JHKelm2011AccMem,
 author="John H. Kelm and Daniel R. Johnson and William Tuohy and Steven S. Lumetta and Sanjay J. Patel",
 title="Cohesion: An adaptive hybrid memory model for accelerators",
 journal="IEEE Micro",
 year="2011",
 month="Jan./Feb.)",
 volume="31",
 number="1",
 pages="42-55",
}

@article{MiloMKMartin2012scale,
 author="Milo M. K. Martin and Mark D. Hill and Daniel J. Sorin",
 title="Why On-Chip Coherence Is Here to Stay",
 Year="2012",
 journal="Communications of the ACM",
 volume="55",
 number="7",
 month="July",
 pages="78-89",
 doi="10.1145/2209249.2209269",
}

@book{DanielJSorin2011MemModel,
 title="A Primer on Memory Consistency and Cache Coherence",
 author="Daniel J. Sorin and Mark D. Hill and David A. Wood",
 publisher="Morgan \& Claypool",
 year="2011",
 isbn="9781608455645",
 series="Synthesis Lectures on Computer Architecture",
 doi="10.2200/S00346ED1V01Y201104CAC016",
}

@article{Kim:2014:FBM:2678373.2665726,
 author = {Kim, Yoongu and Daly, Ross and Kim, Jeremie and Fallin, Chris and Lee, Ji Hye and Lee, Donghyuk and Wilkerson, Chris and Lai, Konrad and Mutlu, Onur},
 title = {Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors},
 journal = {SIGARCH Comput. Archit. News},
 issue_date = {June 2014},
 volume = {42},
 number = {3},
 month = jun,
 year = {2014},
 issn = {0163-5964},
 pages = {361--372},
 numpages = {12},
 url = {http://doi.acm.org/10.1145/2678373.2665726},
 doi = {10.1145/2678373.2665726},
 acmid = {2665726},
 publisher = {ACM},
 address = {New York, NY, USA},
}

@unpublished{PaulEMcKenney2016LinuxKernelMMIO,
 Author="Paul E. McKenney and Will Deacon and Luis R. Rodriguez",
 Title="Semantics of {MMIO} mapping attributes across architectures",
 month="August",
 day="24",
 year="2016",
 note="\url{https://lwn.net/Articles/698014/}",
}

@unpublished{JannHorn2018MeltdownSpectre,
 Author="Jann Horn",
 Title="Reading privileged memory with a side-channel",
 month="January",
 day="3",
 year="2018",
 note="\url{https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html}",
}