| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| * |
| * Copyright (C) 2025 Renesas Electronics Corp. |
| */ |
| |
| #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ |
| #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ |
| |
| #include <dt-bindings/clock/renesas-cpg-mssr.h> |
| |
| /* R9A09G077 CPG Core Clocks */ |
| #define R9A09G077_CLK_CA55C0 0 |
| #define R9A09G077_CLK_CA55C1 1 |
| #define R9A09G077_CLK_CA55C2 2 |
| #define R9A09G077_CLK_CA55C3 3 |
| #define R9A09G077_CLK_CA55S 4 |
| #define R9A09G077_CLK_CR52_CPU0 5 |
| #define R9A09G077_CLK_CR52_CPU1 6 |
| #define R9A09G077_CLK_CKIO 7 |
| #define R9A09G077_CLK_PCLKAH 8 |
| #define R9A09G077_CLK_PCLKAM 9 |
| #define R9A09G077_CLK_PCLKAL 10 |
| #define R9A09G077_CLK_PCLKGPTL 11 |
| #define R9A09G077_CLK_PCLKH 12 |
| #define R9A09G077_CLK_PCLKM 13 |
| #define R9A09G077_CLK_PCLKL 14 |
| #define R9A09G077_SDHI_CLKHS 15 |
| |
| #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ |
