| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * dts file for Hisilicon Hi3670 SoC |
| * |
| * Copyright (C) 2016, Hisilicon Ltd. |
| * Copyright (C) 2018, Linaro Ltd. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/hi3670-clock.h> |
| |
| / { |
| compatible = "hisilicon,hi3670"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| cluster1 { |
| core0 { |
| cpu = <&cpu4>; |
| }; |
| core1 { |
| cpu = <&cpu5>; |
| }; |
| core2 { |
| cpu = <&cpu6>; |
| }; |
| core3 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| }; |
| |
| cpu2: cpu@2 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| }; |
| |
| cpu3: cpu@3 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| }; |
| |
| cpu4: cpu@100 { |
| compatible = "arm,cortex-a73"; |
| device_type = "cpu"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| }; |
| |
| cpu5: cpu@101 { |
| compatible = "arm,cortex-a73"; |
| device_type = "cpu"; |
| reg = <0x0 0x101>; |
| enable-method = "psci"; |
| }; |
| |
| cpu6: cpu@102 { |
| compatible = "arm,cortex-a73"; |
| device_type = "cpu"; |
| reg = <0x0 0x102>; |
| enable-method = "psci"; |
| }; |
| |
| cpu7: cpu@103 { |
| compatible = "arm,cortex-a73"; |
| device_type = "cpu"; |
| reg = <0x0 0x103>; |
| enable-method = "psci"; |
| }; |
| }; |
| |
| gic: interrupt-controller@e82b0000 { |
| compatible = "arm,gic-400"; |
| reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ |
| <0x0 0xe82b2000 0 0x2000>, /* GICC */ |
| <0x0 0xe82b4000 0 0x2000>, /* GICH */ |
| <0x0 0xe82b6000 0 0x2000>; /* GICV */ |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | |
| IRQ_TYPE_LEVEL_HIGH)>; |
| interrupt-controller; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | |
| IRQ_TYPE_LEVEL_LOW)>; |
| clock-frequency = <1920000>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| crg_ctrl: crg_ctrl@fff35000 { |
| compatible = "hisilicon,hi3670-crgctrl", "syscon"; |
| reg = <0x0 0xfff35000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| crg_rst: crg_rst_controller { |
| compatible = "hisilicon,hi3670-reset", |
| "hisilicon,hi3660-reset"; |
| #reset-cells = <2>; |
| hisi,rst-syscon = <&crg_ctrl>; |
| }; |
| |
| pctrl: pctrl@e8a09000 { |
| compatible = "hisilicon,hi3670-pctrl", "syscon"; |
| reg = <0x0 0xe8a09000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| pmuctrl: crg_ctrl@fff34000 { |
| compatible = "hisilicon,hi3670-pmuctrl", "syscon"; |
| reg = <0x0 0xfff34000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| sctrl: sctrl@fff0a000 { |
| compatible = "hisilicon,hi3670-sctrl", "syscon"; |
| reg = <0x0 0xfff0a000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| iomcu: iomcu@ffd7e000 { |
| compatible = "hisilicon,hi3670-iomcu", "syscon"; |
| reg = <0x0 0xffd7e000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| media1_crg: media1_crgctrl@e87ff000 { |
| compatible = "hisilicon,hi3670-media1-crg", "syscon"; |
| reg = <0x0 0xe87ff000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| media2_crg: media2_crgctrl@e8900000 { |
| compatible = "hisilicon,hi3670-media2-crg","syscon"; |
| reg = <0x0 0xe8900000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| uart0: serial@fdf02000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xfdf02000 0x0 0x1000>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>, |
| <&crg_ctrl HI3670_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@fdf00000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xfdf00000 0x0 0x1000>; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>, |
| <&crg_ctrl HI3670_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| pinctrl-names = "default"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@fdf03000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xfdf03000 0x0 0x1000>; |
| interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>, |
| <&crg_ctrl HI3670_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@ffd74000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xffd74000 0x0 0x1000>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>, |
| <&crg_ctrl HI3670_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@fdf01000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xfdf01000 0x0 0x1000>; |
| interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>, |
| <&crg_ctrl HI3670_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@fdf05000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xfdf05000 0x0 0x1000>; |
| interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>, |
| <&crg_ctrl HI3670_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| pinctrl-names = "default"; |
| status = "disabled"; |
| }; |
| |
| uart6: serial@fff32000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xfff32000 0x0 0x1000>; |
| interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg_ctrl HI3670_CLK_UART6>, |
| <&crg_ctrl HI3670_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; |
| status = "disabled"; |
| }; |
| |
| gpio0: gpio@e8a0b000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a0b000 0x0 0x1000>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO0>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio1: gpio@e8a0c000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a0c000 0x0 0x1000>; |
| interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO1>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio2: gpio@e8a0d000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a0d000 0x0 0x1000>; |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 1 6 7>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO2>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio3: gpio@e8a0e000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a0e000 0x0 0x1000>; |
| interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO3>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio4: gpio@e8a0f000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a0f000 0x0 0x1000>; |
| interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 18 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO4>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio5: gpio@e8a10000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a10000 0x0 0x1000>; |
| interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 26 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO5>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio6: gpio@e8a11000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a11000 0x0 0x1000>; |
| interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 1 34 7>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO6>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio7: gpio@e8a12000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a12000 0x0 0x1000>; |
| interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 41 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO7>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio8: gpio@e8a13000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a13000 0x0 0x1000>; |
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 49 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO8>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio9: gpio@e8a14000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a14000 0x0 0x1000>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 57 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO9>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio10: gpio@e8a15000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a15000 0x0 0x1000>; |
| interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 65 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO10>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio11: gpio@e8a16000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a16000 0x0 0x1000>; |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 73 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO11>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio12: gpio@e8a17000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a17000 0x0 0x1000>; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 81 1>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO12>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio13: gpio@e8a18000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a18000 0x0 0x1000>; |
| interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO13>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio14: gpio@e8a19000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a19000 0x0 0x1000>; |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO14>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio15: gpio@e8a1a000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a1a000 0x0 0x1000>; |
| interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO15>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio16: gpio@e8a1b000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a1b000 0x0 0x1000>; |
| interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx5 0 0 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO16>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio17: gpio@e8a1c000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a1c000 0x0 0x1000>; |
| interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx5 0 8 2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO17>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio18: gpio@fff28000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xfff28000 0x0 0x1000>; |
| interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx1 4 42 4>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&sctrl HI3670_PCLK_GPIO18>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio19: gpio@fff29000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xfff29000 0x0 0x1000>; |
| interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx1 0 61 2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&sctrl HI3670_PCLK_GPIO19>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio20: gpio@e8a1f000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a1f000 0x0 0x1000>; |
| interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx7 0 0 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO20>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio21: gpio@e8a20000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xe8a20000 0x0 0x1000>; |
| interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx7 0 8 4>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg_ctrl HI3670_PCLK_GPIO21>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio22: gpio@fff0b000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xfff0b000 0x0 0x1000>; |
| interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| /* GPIO176 */ |
| gpio-ranges = <&pmx1 2 0 6>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&sctrl HI3670_PCLK_AO_GPIO0>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio23: gpio@fff0c000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xfff0c000 0x0 0x1000>; |
| interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| /* GPIO184 */ |
| gpio-ranges = <&pmx1 0 6 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&sctrl HI3670_PCLK_AO_GPIO1>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio24: gpio@fff0d000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xfff0d000 0x0 0x1000>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| /* GPIO192 */ |
| gpio-ranges = <&pmx1 0 14 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&sctrl HI3670_PCLK_AO_GPIO2>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio25: gpio@fff0e000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xfff0e000 0x0 0x1000>; |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| /* GPIO200 */ |
| gpio-ranges = <&pmx1 0 22 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&sctrl HI3670_PCLK_AO_GPIO3>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio26: gpio@fff0f000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xfff0f000 0x0 0x1000>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| /* GPIO208 */ |
| gpio-ranges = <&pmx1 0 30 1>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&sctrl HI3670_PCLK_AO_GPIO4>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio27: gpio@fff10000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xfff10000 0x0 0x1000>; |
| interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| /* GPIO216 */ |
| gpio-ranges = <&pmx1 4 31 4>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&sctrl HI3670_PCLK_AO_GPIO5>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| gpio28: gpio@fff1d000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xfff1d000 0x0 0x1000>; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx1 1 35 7>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&sctrl HI3670_PCLK_AO_GPIO6>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| /* UFS */ |
| ufs: ufs@ff3c0000 { |
| compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; |
| /* 0: HCI standard */ |
| /* 1: UFS SYS CTRL */ |
| reg = <0x0 0xff3c0000 0x0 0x1000>, |
| <0x0 0xff3e0000 0x0 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, |
| <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; |
| clock-names = "ref_clk", "phy_clk"; |
| freq-table-hz = <0 0>, <0 0>; |
| /* offset: 0x84; bit: 12 */ |
| resets = <&crg_rst 0x84 12>; |
| reset-names = "rst"; |
| }; |
| |
| /* SD */ |
| dwmmc1: dwmmc1@ff37f000 { |
| compatible = "hisilicon,hi3670-dw-mshc", |
| "hisilicon,hi3660-dw-mshc"; |
| reg = <0x0 0xff37f000 0x0 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg_ctrl HI3670_CLK_GATE_SD>, |
| <&crg_ctrl HI3670_HCLK_GATE_SD>; |
| clock-names = "ciu", "biu"; |
| clock-frequency = <3200000>; |
| resets = <&crg_rst 0x94 18>; |
| reset-names = "reset"; |
| hisilicon,peripheral-syscon = <&sctrl>; |
| card-detect-delay = <200>; |
| status = "disabled"; |
| }; |
| |
| /* SDIO */ |
| dwmmc2: dwmmc2@fc183000 { |
| compatible = "hisilicon,hi3670-dw-mshc", |
| "hisilicon,hi3660-dw-mshc"; |
| reg = <0x0 0xfc183000 0x0 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>, |
| <&crg_ctrl HI3670_HCLK_GATE_SDIO>; |
| clock-names = "ciu", "biu"; |
| clock-frequency = <3200000>; |
| resets = <&crg_rst 0x94 20>; |
| reset-names = "reset"; |
| card-detect-delay = <200>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
