| 0d34dfbf3023 ("clk: tegra210: fix PLLU and PLLU_OUT1") | |
| e745f992cf4b ("clk: tegra: Rework pll_u") | |
| 3843832fc8ca ("clk: tegra: Handle UTMIPLL IDDQ") | |
| 24c3ebef1ab6 ("clk: tegra: Add aclk") | |
| 319af7975c9f ("clk: tegra: Define Tegra210 DMIC sync clocks") | |
| bfa34832df1f ("clk: tegra: Add CEC clock") | |
| 8dce89a1c2cf ("clk: tegra: Don't warn for PLL defaults unnecessarily") | |
| 34ac2c278b30 ("clk: tegra: Fix ISP clock modelling") | |
| 9326947f2215 ("clk: tegra: Fix pll_a1 iddq register, add pll_a1") |