| 2b5cf4ef541f ("drm/i915/dp_mst: Fix enabling pipe clock for all streams") |
| bc334d914eee ("drm/i915/icl: toggle PHY clock gating around link training") |
| 340a44bef234 ("drm/i915/icl: program MG_DP_MODE") |
| afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders") |
| 24a28179ecc0 ("drm/i915/ddi: s/crtc->config/old_crtc_state in haswell_crtc_disable()") |
| c8af5274c3cb ("drm/i915: enable the pipe/transcoder/planes later on HSW+") |
| c27e917e2bda ("drm/i915/icl: add basic support for the ICL clocks") |
| fb5c8e9d4350 ("drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI") |
| be1c63c8017b ("drm/i915/dp: Send DPCD ON for MST before phy_up") |
| c92f47b5ec97 ("drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI") |
| ad260ab32a4d ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.") |
| 2320175feb74 ("drm/i915: Implement HDCP for HDMI") |
| 8edcda1266f9 ("drm/i915: Protect DDI port to DPLL map from theoretical race.") |
| c249f1f423ea ("drm/i915: Eliminate crtc->config usage from CRT code") |
| 1939ba51fd05 ("drm/i915: Pass a crtc state to ddi post_disable from MST code") |
| f3cf4ba45e13 ("drm/i915: Pass encoder type to cnl_ddi_vswing_sequence() explicitly") |
| 45e0327e28e5 ("drm/i915: Plumb crtc_state etc. directly to intel_ddi_pre_enable_{dp,hdmi}()") |
| 680b71c201fc ("drm/i915: Remove useless eDP check from intel_ddi_pre_enable_dp()") |
| f45f3da7c4f6 ("drm/i915: Split intel_ddi_post_disable() into DP vs. HDMI variants") |
| e725f6456f6f ("drm/i915: Extract intel_disable_ddi_buf()") |
| 6b8506d575e3 ("drm/i915: Extract intel_ddi_clk_disable()") |
| 2de3813880bf ("drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare") |
| 27d81c28eef1 ("drm/i915: push DDI FDI link training on enable to CRT encoder") |
| 364a3fe18235 ("drm/i915: push DDI and DSI underrun reporting on enable to encoder") |
| 3daa3cee6ebc ("drm/i915: push DDI CRT underrun reporting on disable to encoder") |
| 51c4fa6903f9 ("drm/i915: push DDI CRT underrun reporting on enable to encoder") |
| 5ea2355a100a ("drm/i915/mst: Use MST sideband message transactions for dpms control") |
| ed69cd40685c ("drm/i915/glk, cnl: Implement WaDisableScalarClockGating") |
| 9b1c581885c9 ("drm/i915/mst: Print active mst links after update") |
| cf3e0fb48cdb ("drm/i915/cnl: Move ddi buf trans related functions up.") |
| cc9cabfdec38 ("drm/i915/cnl: Move voltage check into ddi buf trans functions.") |
| 381f957044d0 ("drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.") |
| 2f7460a75aa4 ("drm/i915: Align vswing sequences with old ddi buffer registers.") |
| d509af6c85bb ("drm/i915: decouple gen9 and gen10 dp signal levels.") |
| 1b6e2fd2896a ("drm/i915: Introduce intel_ddi_dp_level.") |
| 5f88a9c61978 ("drm/i915: Constify states passed to enable/disable/etc. encoder hooks") |
| f99be1b322cc ("drm/i915: Move infoframe vfuncs into intel_digital_port") |
| c5f93fcf2ee1 ("drm/i915: Disable infoframes when shutting down DDI HDMI") |
| b47ef0f793d9 ("drm/i915: Check has_infoframes when enabling infoframes") |
| 50946c89850d ("drm/i915: Return correct EDP voltage swing table for 0.85V") |
| 2901215920aa ("drm/i915: Pass enum pipe to intel_set_pch_fifo_underrun_reporting()") |
| 61f3e7704897 ("drm/i915/cnl: Add missing type case.") |
| 0091abc3a621 ("drm/i915/cnl: Enable loadgen_select bit for vswing sequence") |
| cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.") |
| 04416108ccea ("drm/i915/cnl: Add registers related to voltage swing sequences.") |
| a927c927de34 ("drm/i915/cnl: Initialize PLLs") |
| 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping") |
| d8d4a512a6ff ("drm/i915/cnl: Implement CNL display init/unit sequence") |
| ef4f7a689ac5 ("drm/i915/cnl: Implement .set_cdclk() for CNL") |
| 945f2672ccbb ("drm/i915/cnl: Implement .get_display_clock_speed() for CNL") |
