| 44ce0cd3b514 ("drm/amd/display: move dispclk vco freq to clk mgr base") |
| 44e149bb1ea2 ("drm/amdgpu/display: clean up dcn2*_pp_smu functions") |
| 976035dd4f68 ("drm/amd/display: add renoir specific watermark range and clk helper") |
| a51894f015af ("drm/amd/display: hook up notify watermark ranges and get clock table") |
| 9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off") |
| 7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot") |
| 799c5b9cb91c ("drm/amd/display: Revert fixup DPP programming sequence") |
| a45804db8bc0 ("drm/amd/display: Replace for loop w/ function call") |
| b6e881c94741 ("drm/amd/display: update navi to use new surface programming behaviour") |
| 6f4e6361c3ff ("drm/amd/display: Add Renoir resource (v2)") |
| 4edb6fc91878 ("drm/amd/display: Add Renoir clock manager") |
| 6f451b60e044 ("drm/amd/display: Add Renoir Hubbub (v2)") |
| eced51f9babb ("drm/amd/display: Add hubp block for Renoir (v2)") |
| 285e30049708 ("drm/amd/display: fix dcn20 odm dpp programming") |
| b1f6d01c4a3b ("drm/amd/display: re structure odm to allow 4 to 1 support") |
| 4c3cfe14c04e ("Revert "drm/amd/display: add global master update lock for DCN2"") |
| 675a9e38b39c ("drm/amd/display: Load NV12 SOC BB from firmware") |
| e7f2c80cbaab ("drm/amd/display: check hpd before retry verify link cap") |
| 544618596fd5 ("drm/amd/display: wake up ogam mem pwr before programming ocsc") |
| b5b1f4554904 ("drm/amd/display: Enable type C hotplug") |
| 2b162fd30249 ("drm/amd/display: update optc odm interface for more than 2 opps") |
| c681491a0921 ("drm/amd/display: fix pipe selection logic in validate") |
| 1a9e3d4569fc ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end") |
| b9e8d95a7bc2 ("drm/amd/display: clean up DML for DCN2x") |
| 5ec43eda8550 ("drm/amd/display: enabling seamless boot sequence for dcn2") |
| 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") |
| 986936d1a9b2 ("drm/amd/display: wait for pending complete when enabling a plane") |
| 37495fbdf12d ("drm/amd/display: Add work-around option to skip DCN20 clock updates") |
| f7f38ffef56b ("drm/amd/display: fixup DPP programming sequence") |
| 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create") |
| ac42fd639550 ("drm/amd/display: reset hdmi tmds rate and data scramble on pipe reset") |
| f16d523f9d83 ("drm/amd/display: Support uclk switching for DCN2") |
| fb6959ae5017 ("drm/amd/display: Embed DCN2 SOC bounding box") |
| d3b9f39d8417 ("drm/amdgpu/display: fix the build without CONFIG_DRM_AMD_DC_DSC_SUPPORT") |
| 21ffcc94d5b3 ("drm/amd/display: Copy GSL groups when committing a new context") |
| 057fc695e934 ("drm/amd/display: support "dummy pstate"") |
| dcbb45b6eeed ("drm/amd/display: do not read link setting if edp not connected") |
| f591344e89dc ("drm/amd/display: Clean up dynamic metadata logic") |
| 39bca3599aab ("drm/amd/display: add a option to force the clock at every mode change.") |
| 925f566cb7ae ("drm/amd/display: add set and get clock for testing purposes") |
| 290129c25617 ("drm/amd/display: Add CM_BYPASS via debug option") |
| 70f1476a7eed ("drm/amd/display: Add debug option to disable timing sync") |
| c43f89f81cc0 ("drm/amd/display: put back front end initialization sequence") |
| 75c35000235f ("drm/amd/display: Power-gate all DSCs at driver init time") |
| 24f1d1cee2bc ("drm/amd/display: Check for valid stream_encode") |
| 606b355170b5 ("drm/amd/display: add hdmi2.1 dsc pps packet programming") |
| 6de202373bf6 ("drm/amd/display: move bw calc code into helpers") |
| ec16ac6b4264 ("drm/amd/display: fix dsc disable") |
| e0a6440a2961 ("drm/amd/display: Add ability to set preferred link training parameters.") |
| 93c25fbdc30a ("drm/amd/display: initialize p_state to proper value") |
