| 47aa1e73e72e ("drm/i915: move dpll_info to header") |
| 294591cfbd2b ("drm/i915: Update kerneldoc for intel_dpll_mgr.c") |
| eac6176cbdcb ("drm/i915: Rename intel_shared_dpll->mode_set() to prepare()") |
| 2c42e5351445 ("drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_state") |
| 3c0fb58820ac ("drm/i915: Rename intel_shared_dpll_commit() to _swap_state()") |
| a1c414ee82d9 ("drm/i915: Introduce intel_release_shared_dpll()") |
| e62929b3f628 ("drm/i915/gen9+: Program watermarks as a separate step during evasion, v3.") |
| ccf010fb943a ("drm/i915: Add an atomic evasion step to watermark programming, v4.") |
| bb7265197a86 ("drm/i915: Pass dev_priv to ilk_setup_wm_latency() & co.") |
| 432081bcbf9a ("drm/i915: Pass intel_crtc to update_wm functions") |
| 2c4b49a0f73f ("drm/i915: Use macro in place of open-coded for_each_universal_plane loop") |
| ed37892e6df2 ("drm/i915: Address broxton phy registers based on phy and channel number") |
| e7583f7b1018 ("drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info") |
| 842d416654eb ("drm/i915: Create a struct to hold information about the broxton phys") |
| b6e08203cc1f ("drm/i915: Move broxton vswing sequence to intel_dpio_phy.c") |
| f38861b814b5 ("drm/i915: Move DPIO phy documentation section to intel_dpio_phy.c") |
| 47a6bc61b866 ("drm/i915: Move broxton phy code to intel_dpio_phy.c") |
| b284eedaf74b ("drm/i915: Pass lane count to bxt_ddi_phy_calc_lane_optmin_mask()") |
| 362624c9ba3f ("drm/i915: Explicitly map broxton DPIO power wells to phys") |
| 01c3faa70bcd ("drm/i915: Rename struct i915_power_well field data to id") |
| d8c0fafcbd68 ("drm/i915/gen9: Get rid of redundant watermark values") |
| ee3d532fcb64 ("drm/i915/gen9: unconditionally apply the memory bandwidth WA") |
| 1bab7502dde2 ("drm/i915/gen9: Cleanup skl_pipe_wm_active_state") |
| a62163e97baf ("drm/i915/gen9: Make skl_wm_level per-plane") |
| b707aa504146 ("drm/i915/skl: Remove linetime from skl_wm_values") |
| ce0ba283f64e ("drm/i915/skl: Move per-pipe ddb allocations into crtc states") |
| 5db9401983ac ("drm/i915: Make IS_GEN macros only take dev_priv") |
| 11a914c28679 ("drm/i915: Make IS_VALLEYVIEW only take dev_priv") |
| 920a14b24597 ("drm/i915: Make IS_CHERRYVIEW only take dev_priv") |
| e2d214ae2b34 ("drm/i915: Make IS_BROXTON only take dev_priv") |
| d9486e65010f ("drm/i915: Make IS_SKYLAKE only take dev_priv") |
| 0853723b8956 ("drm/i915: Make IS_KABYLAKE only take dev_priv") |
| 772c2a519cec ("drm/i915: Make IS_HASWELL only take dev_priv") |
| 8652744b647e ("drm/i915: Make IS_BROADWELL only take dev_priv") |
| fd6b8f43c9e9 ("drm/i915: Make IS_IVYBRIDGE only take dev_priv") |
| 50a0bc905416 ("drm/i915: Make INTEL_DEVID only take dev_priv") |
| 6e266956a57f ("drm/i915: Make INTEL_PCH_TYPE & co only take dev_priv") |
| 4f8036a28112 ("drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv") |
| 3b3f1650b1ca ("drm/i915: Allocate intel_engine_cs structure only for the enabled engines") |
| fc4c79c37e82 ("drm/i915: Consolidate error object printing") |
| 0e70447605f4 ("drm/i915: Move common code out of i915_gpu_error.c") |
| c0c8b9ed1b0c ("Merge tag 'drm-for-v4.9' into drm-intel-next-queued") |
