| 59cd826fb5e7 ("drm/i915: Fix PCH reference clock for FDI on HSW/BDW") |
| 6ce1c33d6c36 ("drm/i915: Kill INTEL_SUBPLATFORM_AML") |
| c3ad8d29db5e ("drm/i915: Add missing commas to the end of the subplatform ID arrays") |
| 4a95e36f0357 ("drm/i915: Rename HSW/BDW PLL bits") |
| b16c7ed95caf ("drm/i915: Do not touch the PCH SSC reference if a PLL is using it") |
| 805446c8347c ("drm/i915: Introduce concept of a sub-platform") |
| d938da6b132a ("drm/i915: Disable C3 when enabling vblank interrupts on i945gm") |
| 57b1c4460dc4 ("drm/i915: Mark AML 0x87CA as ULX") |
| cbecbccaa120 ("drm/i915: Record platform specific ppGTT size in intel_device_info") |
| 37fbbd49054b ("drm/i915: Populate pipe_offsets[] & co. accurately") |
| b2ae318acdca ("drm/i915: Rename HAS_GMCH") |
| 2b34e562361f ("drm/i915/icl: Work around broken VBTs for port F detection") |
| 990290d124d5 ("drm/i915/dpll_mgr: switch to kernel types") |
| 3f2e9ed0b26d ("drm/i915/icl: Detect port F presence via VBT") |
| 0e6e0be4c952 ("drm/i915: Markup paired operations on display power domains") |
| a037121c3c7f ("drm/i915: Mark up debugfs with rpm wakeref tracking") |
| 506d1f62454b ("drm/i915: Track GT wakeref") |
| 16e4dd0342a8 ("drm/i915: Markup paired operations on wakerefs") |
| bd780f37a361 ("drm/i915: Track all held rpm wakerefs") |
| f663b0ca9b7d ("drm/i915/selftests: recreate WA lists inside the selftest") |
| d25f71a162a9 ("drm/i915: Return immediately if trylock fails for direct-reclaim") |
| 55277e1f3107 ("drm/i915: Always try to reset the GPU on takeover") |
| 1787a98439cc ("drm/i915: drop intel_device_info_dump()") |
| a0f04cc27c50 ("drm/i915: always use INTEL_INFO() to access device info") |
| 1400cc7e0dcd ("drm/i915: pass dev_priv to intel_device_info_runtime_init()") |
| ed5eb1b78a88 ("drm/i915/reg: abstract display_mmio_offset access") |
| 0258404f9d38 ("drm/i915: start moving runtime device info to a separate struct") |
| 6faf5916e6be ("drm/i915: Remove HW semaphores for gen7 inter-engine synchronisation") |
| 167bc759e823 ("drm/i915: Restrict PSMI context load w/a to Haswell GT1") |
| f513ac76530c ("drm/i915/icl: Mind the SFC units when resetting VD or VEBox engines") |
| 57b19d55189b ("drm/i915/icl: Record the valid VDBoxes with SFC capability") |
| 921f3a60e54e ("drm/i915/selftests: Verify we can perform resets from atomic context") |
| 5edd56d394dc ("drm/i915/selftests: Check we can recover a wedged device") |
| f3ce44a09a15 ("drm/i915: merge gen checks to use range") |
| cf819eff907a ("drm/i915: replace IS_GEN<N> with IS_GEN(..., N)") |
| 006900087727 ("drm/i915: Rename IS_GEN to IS_GEN_RANGE") |
| e6154e4cb8b0 ("drm/i915: Skip the ERR_PTR error state") |
| 3abd6143f971 ("drm/i915/selftests: verify_gt_engine_wa() needs rpm wakeref") |
| d15f9cdd59ba ("drm/i915/icl: Do not change reserved registers related to PSR2") |
| 517974992593 ("drm/i915: Allocate a common scratch page") |
| 452420d22d5b ("drm/i915: Fuse per-context workaround handling with the common framework") |
| 69bcdecf1af5 ("drm/i915: Move register white-listing to the common workaround framework") |
| 28d6ccce73be ("drm/i915/selftests: Add tests for GT and engine workaround verification") |
| 094304beb4e1 ("drm/i915: Verify GT workaround state after GPU init") |
| 4a15c75c4246 ("drm/i915: Introduce per-engine workarounds") |
| 25d140faaa25 ("drm/i915: Record GT workarounds in a list") |
| 3800960afe15 ("drm/i915: Complete the fences as they are cancelled due to wedging") |
| d53db442db36 ("drm/i915: Move display device info capabilities to its own struct") |
| e1bf094b3c75 ("drm/i915: Add HAS_DISPLAY() and use it") |
| ab8411483a3e ("drm/i915/icl: Get HW state for DSI encoder") |
