| 6f44610c30c5 ("clk: renesas: r8a77970: Add RPC clocks") |
| 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI") |
| b9d0b84b3db8 ("clk: renesas: rcar-gen3: Add support for RCKSEL clock selection") |
| 38c79e2899a6 ("clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider") |
| 41ceeb5fef77 ("clk: renesas: rcar-gen3: Add Z2 clock divider support") |
| 3391891fa9c8 ("clk: renesas: rcar-gen3: Add Z clock divider support") |
| 9f55b17ff638 ("clk: renesas: rcar-gen3: Restore SDHI clocks during resume") |
| 8d46e28fb508 ("clk: renesas: cpg-mssr: Add R8A77970 support") |
| d71e851d82c6 ("clk: renesas: cpg-mssr: Add R8A77995 support") |
| 696997e004d4 ("clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks") |
| 09a7dea9d58a ("clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3") |
| 2d6f25774332 ("clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table") |
| f317880c5b2b ("clk: renesas: rcar-gen3-cpg: Drop superfluous variable") |
| 4013047a65b3 ("clk: renesas: cpg-mssr: Document R-Car Gen2 support") |
| 80978a4be267 ("clk: renesas: Rework Kconfig and Makefile logic") |
| dcf6a00dffee ("clk: renesas: Do not build clk-div6 for R8A7792") |
| bb1953067c05 ("clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0") |
| 48d0341e4187 ("clk: renesas: cpg-mssr: Add support for fixing up clock tables") |
| cecbe87d7300 ("clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0") |
| 5f3a432a44b1 ("clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()") |
| 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support") |
| c0b2d75d2a4b ("clk: renesas: cpg-mssr: Add R8A7743 support") |
| 30ad3cf00e94 ("clk: renesas: rcar-gen3-cpg: Always use readl()/writel()") |
