| 73c0fcac97bf ("drm/i915: Enable VBT based BL control for DP") |
| 46bd8383d8c9 ("drm/i915: Clean up PPS code calling conventions") |
| 8f4f27970723 ("drm/i915: Nuke intel_digital_port->port") |
| adc103047e58 ("drm/i915: Eliminate some encoder->crtc usage from DP code") |
| 436009b578ab ("drm/i915/cnl: Force DDI_A_4_LANES when needed.") |
| 081dfcfafcbb ("drm/i915: Pass the encoder type explicitly to skl_set_iboost()") |
| 975786ee0e25 ("drm/i915: Extract intel_ddi_get_buf_trans_hdmi()") |
| d8fe2c7f3365 ("drm/i915: Relocate intel_ddi_get_buf_trans_*() functions") |
| 1210d3889077 ("drm/i915: Use bdw_ddi_translations_fdi for Broadwell") |
| 1a8ff6076e8f ("drm/i915: Reorganize .disable hooks for pre-DDI DP") |
| 76a4b41d654c ("drm/i915: Drop useless HAS_PSR() check") |
| bf5035564579 ("drm/i915/cnl: Fix DDI hdmi level selection.") |
| cf3e0fb48cdb ("drm/i915/cnl: Move ddi buf trans related functions up.") |
| cc9cabfdec38 ("drm/i915/cnl: Move voltage check into ddi buf trans functions.") |
| 2f7460a75aa4 ("drm/i915: Align vswing sequences with old ddi buffer registers.") |
| d509af6c85bb ("drm/i915: decouple gen9 and gen10 dp signal levels.") |
| 1b6e2fd2896a ("drm/i915: Introduce intel_ddi_dp_level.") |
| d2419ffc10e4 ("drm/i915: Plumb crtc_state to PSR enable/disable") |
| f761bef2f341 ("drm/i915: Introduce intel_hpd_pin function.") |
| 256cfdde42c0 ("drm/i915: Simplify hpd pin to port") |
| d907b6658a7b ("drm/i915/cnl: Add allowed DP rates for Cannonlake.") |
| 50946c89850d ("drm/i915: Return correct EDP voltage swing table for 0.85V") |
| 93e5f0b65ab8 ("drm/i915: Make intel_digital_port_connected() work for any port") |
| da411a48bdeb ("drm/i915/cfl: Basic DDI plumbing for Coffee Lake.") |
| 0091abc3a621 ("drm/i915/cnl: Enable loadgen_select bit for vswing sequence") |
| cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.") |
| d8d4a512a6ff ("drm/i915/cnl: Implement CNL display init/unit sequence") |
| ef4f7a689ac5 ("drm/i915/cnl: Implement .set_cdclk() for CNL") |
| 945f2672ccbb ("drm/i915/cnl: Implement .get_display_clock_speed() for CNL") |
| b037d58f9762 ("drm/i915: Pass crtc_state and connector state to backlight enable/disable functions") |
| 55cfc5808096 ("drm/i915/dp: cache source rates at init") |
| e1cd3325b7a7 ("drm/i915: move the {skl, bxt}_{i, uni}nit_cdclk declarations") |
| b0dd6887029c ("drm/i915/dsi: rename intel_dsi_exec_vbt_sequence to intel_dsi_vbt_exec_sequence") |
| 3f751d6517d2 ("drm/i915/dsi: stop using the drm_panel framework completely") |
| b9e56754ec79 ("drm/i915/dsi: call vbt_panel_get_modes directly instead of via drm_panel") |
| 7967ef6a02c7 ("drm/i915/dsi: remove support for more than one panel driver") |
| 3dc38eea665f ("drm/i915: Remove direct usages of intel_crtc->config from DDI code") |
| e9ce1a625fca ("drm/i915: Pass intel_crtc to DDI functions called from crtc en/disable") |
| 25b4620ee822 ("drm/i915/dsi: Skip delays for v3 VBTs in vid-mode") |
| 38dec5c0892a ("drm/i915/dsi: Call MIPI_SEQ_TEAR_ON and DISPLAY_ON for cmd-mode (untested)") |
| 7108b436c2b5 ("drm/i915/dsi: Execute MIPI_SEQ_TEAR_OFF from intel_dsi_post_disable") |
| f5bce6df8868 ("drm/i915/dsi: Group MIPI_SEQ_BACKLIGHT_ON/OFF with panel_[en|dis]able_backlight") |
| 3e40fa8a3168 ("drm/i915/dsi: Execute MIPI_SEQ_DEASSERT_RESET before calling device_ready()") |
| deae2006a3a8 ("drm/i915/dsi: Group DPOunit clock gate workaround with PLL enable") |
| c7dc5275bcbd ("drm/i915/dsi: Move MIPI_SEQ_POWER_ON/OFF calls together with pmic gpio calls") |
| 19c17df3cb5e ("drm/i915/dsi: Drop bogus MIPI_SEQ_ASSERT_RESET before POWER_ON") |
| 249f69623531 ("drm/i915/dsi: Document the panel enable / disable sequences from the spec") |
| 18a00095a5f3 ("drm/i915/dsi: Make intel_dsi_enable/disable directly exec VBT sequences") |
| 5a2e65e742ca ("drm/i915/dsi: Merge intel_dsi_disable/enable into their respective callers") |
| 3870b89a810b ("drm/i915/dsi: Move calling of wait_for_dsi_fifo_empty to mipi_exec_send_packet") |
