| 7487508eff1f ("drm/i915: protect macro parameters in SWING_SEL_{UPP,LO}WER") |
| 5bb975de3f27 ("drm/i915/icl: Add register definitions for Combo PHY vswing sequences.") |
| da9cb11f7662 ("drm/i915/cnl: Kill _MMIO_PORT6 macro") |
| 4635b573634c ("drm/i915/cnl; Add macro to get PORT_TX register") |
| e103962611b2 ("drm/i915/cnl: Fix PORT_TX_DW5/7 register address") |
| 8f942ed00efe ("drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.") |
| 33b92c1e1f27 ("drm/i915/cnl: Fix RMW on ddi vswing sequence.") |
| cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.") |
| 04416108ccea ("drm/i915/cnl: Add registers related to voltage swing sequences.") |
| 4557c6072724 ("drm/i915: Add MMIO helper for 6 ports with different offsets.") |
| a927c927de34 ("drm/i915/cnl: Initialize PLLs") |
| 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping") |
| d8d4a512a6ff ("drm/i915/cnl: Implement CNL display init/unit sequence") |
| ef4f7a689ac5 ("drm/i915/cnl: Implement .set_cdclk() for CNL") |
| 945f2672ccbb ("drm/i915/cnl: Implement .get_display_clock_speed() for CNL") |
| a1986f4174a4 ("drm/i915: Remove unnecessary PORT3 definition.") |
| e1cd3325b7a7 ("drm/i915: move the {skl, bxt}_{i, uni}nit_cdclk declarations") |
| 62b695662a24 ("drm/i915: Only enable DDI IO power domains after enabling DPLL") |
| 71cc22e5db89 ("drm/i915/glk: Don't enable DDI IO power domains during init") |
| f4f4b59be52b ("drm/i915/glk: Implement WaDDIIOTimeout") |
| ffe5111e28e5 ("drm/i915: Introduce intel_ddi_dp_voltage_max()") |
| 24dbf51a5517 ("drm/i915: struct_mutex is not required for allocating the framebuffer") |
| 70001cd25654 ("drm/i915: Remove struct_mutex for destroying framebuffers") |
| 370a81fb89cb ("drm/i915: Remove unused function intel_ddi_get_link_dpll()") |
| d8fc70b7367b ("drm/i915: Make power domain masks 64 bit long") |
| 49cd97a35d90 ("drm/i915: Start moving the cdclk stuff into a distinct state structure") |
| 8f0cfa4d2a62 ("drm/i915: Pass computed vco to bxt_set_cdclk()") |
| 7ff89ca21358 ("drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c") |
| 4717e8bb7341 ("drm/i915: Clean up the .get_cdclk() assignment if ladder") |
| c49a0d054a05 ("drm/i915: s/get_display_clock_speed/get_cdclk/") |
| 4e841ecd4e18 ("drm/i915: Nuke intel_mode_max_pixclk()") |
| a7d1b3f41a2d ("drm/i915: Store the pipe pixel rate in the crtc state") |
| 3c779a49bd7c ("drm/i915: Avoid BIT(max) - 1 and use GENMASK(max - 1, 0)") |
| 6248017ae530 ("drm/i915: Get correct display clock on 945gm") |
| ce64645d86ac ("drm/i915: use variadic macros and arrays to choose port/pipe based registers") |
| 9fb5026f857d ("drm/i915/glk: Turn on workarounds that apply to Geminilake too") |
| b976dc53ec43 ("drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.") |
| 8da53efaa228 ("drm/i915/kbl: Apply WaIncreaseDefaultTLBEntries on KBL.") |
| 32ebc292119a ("drm/i915: Remove BXT restore arbitration around ctx switch") |
| 31bb2ef97ea9 ("drm/i915: Check for NULL atomic state in intel_crtc_disable_noatomic()") |
| a8cd6da0c0d5 ("drm/i915: Remove crtc->config usage from intel_modeset_readout_hw_state()") |
| 1d4258db3e0b ("drm/i915: Remove useless casts to intel_plane_state") |
| 957870f93412 ("drm/i915: Split out i915_gem_object_set_tiling()") |
| 254e0931f5b9 ("drm/i915/glk: Convert a few more IS_BROXTON() to IS_GEN9_LP()") |
| 91d4e0aa923e ("drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c") |
| 944397f04f24 ("drm/i915: Store required fence size/alignment for GGTT vma") |
| 0d4e8f1dbcab ("drm/i915: Replace WARNs in fence register writes with extensive asserts") |
| 5b30694b474d ("drm/i915: Align GGTT sizes to a fence tile row") |
| 6649a0b6501d ("drm/i915: Extract tile_row_size for fencing") |
| ef426c103892 ("Merge tag 'drm-misc-next-2016-12-30' of git://anongit.freedesktop.org/git/drm-misc into drm-intel-next-queued") |
