blob: b05e3d973269f0d2122c00630fe3f6c34931b514 [file] [log] [blame]
88023d43ffe1 ("mmc: sunxi: allow 3.3V DDR when DDR is available")
c903a2ae546a ("mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode")
43c15e962c12 ("mmc: sunxi: Add more debug informations")
9479074e9376 ("mmc: sunxi: Gate the clock when rate is 0")
39cc281fb79e ("mmc: sunxi: Fix clock frequency change sequence")