| 95594cb40c6e ("riscv: move the TLB flush logic out of line") |
| f5bf645d10f2 ("riscv: cleanup riscv_cpuid_to_hartid_mask") |
| eb93685847a9 ("riscv: fix flush_tlb_range() end address for flush_tlb_page()") |
| 9e953cda5cdf ("riscv: Introduce huge page support for 32/64bit kernel") |
| a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") |
| f6635f873a60 ("riscv: move switch_mm to its own file") |
| 58de77545e53 ("riscv: move flush_icache_{all,mm} to cacheflush.c") |
| a3182c91ef4e ("RISC-V: Access CSRs using CSR numbers") |
| df16c40cbfb4 ("riscv: clear all pending interrupts when booting") |
| 2353ecc6f91f ("bpf, riscv: add BPF JIT for RV64G") |
| f99fb607fb2b ("RISC-V: Use Linux logical CPU number instead of hartid") |
| 6825c7a80f18 ("RISC-V: Add logical CPU indexing for RISC-V") |
| a37d56fc4011 ("RISC-V: Use WRITE_ONCE instead of direct access") |
| 177fae451588 ("RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu") |
| b2f8cfa7ac34 ("RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid") |
| 19ccf29bb18f ("RISC-V: Filter ISA and MMU values in cpuinfo") |
| 8237f8bc4f6e ("irqchip: add a SiFive PLIC driver") |
| 94f592f0e5b9 ("RISC-V: Add the directive for alignment of stvec's value") |
| 62b019436814 ("clocksource: new RISC-V SBI timer driver") |
| 6ea0f26a7913 ("RISC-V: implement low-level interrupt handling") |
| b9490350f751 ("RISC-V: remove timer leftovers") |
| 8606544890d7 ("RISC-V: Don't include irq-riscv-intc.h") |
| 6a4d4b3253c1 ("Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux") |
